Boolean in VHDL? When does '0/1' fail?

Question

I was wondering as to why VHDL has a boolean data-type? When does '0' or '1' not cut it? Is boolean implemented differently?

Answer 1

There are many ways to answer your question, but the most important thing to remember is that VHDL was developed by a U.S. Department of Defense committee and therefore we should not expect things like logic or reason-- which is ironic because we're talking about logic.

VHDL is a "strongly typed" language. Normally in a strongly typed language there are many different data types that are similar to each other, but differ only in usage. For example, you could use an integer, SLV, or enumerated data type for a state machine variable. But for most situations only an enum works "optimally".

This method helps to prevent the programmer from introducing bugs, while giving the compiler the most freedom to create optimized code/logic. With a state-variable, the compiler can choose the most optimal state-encoding (one-hot, binary, etc.). If the state variable were implemented as an integer or SLV, the compiler would not have that ability. Also, with integer or SLV you could easily inadvertently assign invalid states to the state variable, creating bugs that can be hard to diagnose.

The same is true for Boolean, although it is harder to see the benefit. It forces the writer to be explicit where, without strong data typing, the code would be less "obvious". Essentially, it's harder to make a mistake with Boolean.

The side effect of strong data types is that some things are more "wordy" in VHDL. It's the price we pay.

But to directly answer your questions...

"When does 0/1 not cut it?" Technically, 0/1 would work. The main problem with 0/1 is that it doesn't tell you which state is "true". Is that signal active low, or active high? You can't get confused with the Boolean TRUE/FALSE. But in all other cases, 0/1 would be perfectly fine. Boolean is there, not for technical reasons, but for logistical programming reasons.

"Is Boolean implemented differently?" Not really. The logic generated isn't any different than the well-written alternative. Again, it's mostly there to keep the programmer from inadvertently doing something stupid.

I should also point out that when discussing strongly vs. weakly typed programming languages things quickly degenerate into a philosophical debate-- and the nuances of this debate cannot be fully understood unless you've written lots of code (1+ million lines of code). Another thing that is frequently overlooked is that there are levels of strongly and weakly typed data. I would describe C and being weakly typed, and C++ as being strongly typed, although tables on Wikipedia show almost every language as strongly typed.

Answer 2

It's a matter of taste to be honest.

In the 1993 LRM there's a note related to BOOLEAN on page 36 which states that

type BOOLEAN can be used to model either active high or active low logic depending on the particular conversion functions chosen to and from type BIT

The implication being that BOOLEAN should be used to described functionality and converted to a "logic-level" later on.

Answer 3

It Is Done For Clarity

I'm sure in every case that you use a boolean, you could use a '0/1'. Personally (when using aptly named variables) I think it just makes for cleaner/more-descriptive code to write something like:

signal OutputEnabled : boolean;

and later refernce it as

if ( not(OutputEnabled) ) then
    Output <= 'Z';
else
    Output <= Input;
end if;

instead of

signal OutputEnabled : std_logic;

and later refernce it as

if ( OutputEnabled /= '1' ) then
    Output <= 'Z';
else
    Output <= Input;
end if;

A great use for booleans is to abstract active-low signals so that I don't have to dig through the code in search for every place that I do a comparison if I have to change the polarity.

New for VHDL-2008

Interestingly enough the new VHDL 2008 standard performs implicit conversions of conditions into boolean for you without any casting, so you could write:

signal OutputEnabled : std_logic;

and later refernce it as

if ( not(OutputEnabled) ) then

Pretty good inclusion in my opinion!

Answer 4

The boolean type is for variables where 0/1 is for signals. I don't specifically know the difference between signals and variables but I believe variables can only be used internally and not routed to external pins, but having variables allows you to perform higher-level tasks that bits dont' suffice for.