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I would like to design a MIPI CSI2 bridge with a MachXO3L.

I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the camera is free-running clock and doesn't handle LP.

This Lattice document explains what I have been following: http://www.latticesemi.com/~/media/LatticeSemi/Documents/ReferenceDesigns/JM/MIPIDPHYInterfaceIP.pdf?document_id=50110

enter image description here

I don't want to deserialize/re-serialize data as the CSI2 traffic speed might be faster than what the MachXO3L can handle digitally. I want to achieve an "analog" bridge. Analog is perhaps not the right term, this is more by opposition to digital with deserialization/re-serialization.

My code looks like the following:

BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;

LOCATE COMP "clk_x1" SITE "C8" ;
FREQUENCY PORT "clk_x1" 12.000000 MHz ;
IOBUF PORT "clk_x1" PULLMODE=NONE IO_TYPE=LVCMOS25 ;


LOCATE COMP "I_CLK" SITE "R11" ;    # PB35A
#LOCATE COMP "I_CLK_N" SITE "T12" ; # PB35B

LOCATE COMP "I_DAT0" SITE "R13" ;   # PB34A
#LOCATE COMP "I_DAT0_N" SITE "T14" ;    # PB34B

IOBUF PORT "I_CLK"  PULLMODE=NONE IO_TYPE=LVDS25 DIFFRESISTOR=100 ;
IOBUF PORT "I_DAT0" PULLMODE=NONE IO_TYPE=LVDS25 DIFFRESISTOR=100 ;


LOCATE COMP "O_CLK" SITE "D10" ;    # PT27A
#LOCATE COMP "O_CLK_N" SITE "E10" ; # PT27B

LOCATE COMP "O_DAT0" SITE "F9" ;    # PT26A
#LOCATE COMP "O_DAT0_N" SITE "E11" ;    # PT26B

IOBUF PORT "O_CLK"  PULLMODE=NONE IO_TYPE=LVDS25 ;
IOBUF PORT "O_DAT0" PULLMODE=NONE IO_TYPE=LVDS25 ;

and also:

module csi_bridge(
    input clk_x1,

    input I_CLK,
    input I_DAT0,

    output O_CLK,
    output O_DAT0,
);

assign O_CLK =  I_CLK;
assign O_DAT0 = I_DAT0;

endmodule

I have tried various things but the processor can't manage to decode the traffic. Obviously, without the FPGA in-between, the processor can decode data.

On the scope, I see things moving on the output side, trying to mimic the input. My scope is not super high bandwidth so I must admit that I have some trouble to say what's really wrong.

Any idea what I should do and what I could be missing? Are they specific Lattice Diamond settings that I should look into?

** EDIT 1 **

To give further details, my objective in the end is to replicate a similar logic to Fairchild FSA642: https://www.fairchildsemi.com/datasheets/FS/FSA642.pdf. I have deeply tested this chip and I'm 100% sure that they don't deserialize/reserialize data because I have swapped clock and data, and it's still working. I'm wondering if I should not remove all resistors and consider all pins independently with an assign logic. Without any pull-up, voltage out won't go higher than voltage in.

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  • \$\begingroup\$ Please give some details: What is the speed of the link? And is it slower than the specified maximum 400 MHz for the LVDS outputs? What is the skew between the two lines introduced by the FPGA? Note that this is by no means an analog circuit. I think you want to say "asynchronous" here. \$\endgroup\$
    – asdfex
    Commented May 8, 2016 at 20:04
  • \$\begingroup\$ Yes, I'm slower than the 400MHz LVDS25 or 450MHz MIPI MachXO3L limit. I have edited the question to clarify "analog" which is probably not the right word indeed. \$\endgroup\$
    – gregoiregentil
    Commented May 8, 2016 at 20:14
  • \$\begingroup\$ The PDF you link uses LVDS25E as transmitters, not LVDS25. That means you configured the outputs wrongly and you are limited to 150 MHz. \$\endgroup\$
    – asdfex
    Commented May 8, 2016 at 20:17
  • \$\begingroup\$ I have tried LVDS25E in lpf file and it's the same: not working. I see that LVDS25E is limited to 150MHz but then why same family datasheet says that MIPI can be up to 450MHz if MIPI is emulated with LVDS25E? Anyway, I don't want to open another thread. \$\endgroup\$
    – gregoiregentil
    Commented May 8, 2016 at 20:38
  • \$\begingroup\$ You can run at 450 MHz when you use the MIPI output standard. In this case you don't need external components afaik. I think one of your problems is skew - the delay between input and output which is not identical on both lines. \$\endgroup\$
    – asdfex
    Commented May 8, 2016 at 20:57

1 Answer 1

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By design a FPGA is digital. So the input camera has to be deserialized before being re-serialized.I have provided further information here. I have provided further information here.

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