How do you design a CMOS buffer with exact same delay of a CMOS inverter?

Question

Everyone knows that a CMOS inverter is simply a PMOS connected to an NMOS. There are situations in asynchronous design that we need to compensate for the inverter propagation delay in a parallel signal running along side of the other signal. In that case I can see that designers add a buffer in gate level schematics.

But I need to implement that buffer by myself using CMOS cell libraries and it seems to me the most rational approach is just to put two inverters in series which inverts the signal twice hence acts like a buffer. But it seems to me that the propagation delay also will be doubled.

How one can have a buffer with EXACT same propagation delay of an inverter?

Answer 1

A common solution is to have to two path as shown in the figure below. The first path is a inverter chain to buffer the signal, or it could be a single inverter if the load is low. The second path is almost identical to first, but one inverter is replaced by a transmission gate like structure.

Using a simulator is should be possible to equalize the delays.

(Please note that the bulk should be tied to ground and vdd for the NMOS and PMOS, respectively. It's not drawn correctly.)

^{simulate this circuit – Schematic created using CircuitLab}

Answer 2

I would suggest an exclusive-or gate. If you tie one input high, you have an inverter. If you tie one input low, you have a buffer. The propagation time should be the same.

Answer 3

One approach is to generate both buffered and inverted signals via the same stage, and there are two classic analog approaches to the problem.

I'll not translate them into CMOS, as I have no expertise at or below the cell library level. They may require matched stages for voltage level conversion before or after the stage itself.

The first is the classic phase splitter: based on a common source amplifier, its gain is approximately -R1/R2, or -1 with equal value resistors. (Component values are otherwise nonsensical). In this form it clearly isn't CMOS, though matched active loads would substitute for the resistors. One drawback is that its maximum voltage swing is only half the supply rail, and the DC level on each output is different.

^{simulate this circuit – Schematic created using CircuitLab}

The second is the long tailed pair, which steers current from one leg to the other. Same remarks apply to replacing resistors with active loads, and nonsensical component values.

I am not convinced it will achieve such good balance of propagation delays, but at least the outputs can be at the same voltage levels and are not limited to half the supply.

^{simulate this circuit}