Altera FPGA Reset System

Question

I having a hard time understanding the best way to setup a NIOS II system with external code and the resets and clocks. One of the reasons why I'd like to figure this out is the JTAG system really struggles and it seems that portions of the system never get reset correctly.

First things first: You need a dual rank synchronizer or some kind of ARST sanitation like this here. So I have that in my HDL code

One question I have is what does the Altera Qsys Clock Source actually do? Does it preform the function of a dual rank syncronizer? Or does it need a sanitized ARST signal? Because in a most systems examples from altera and other suppliers they don't sanitize the ARST and run it straight into the Qsys/NIOS block. (Like in Example 1A below)

The other question that I have is: If I have external code that I connect to the Qsys\NIOS II system what reset signal do I use? Does it need to be reset with the Qsys\NIOS II system? Does the Qsys\NIOS Clock Source do something to the clock signal? Do I have export the Clock and Reset signals from the Qsys system?

Which way is correct? Are there advantages to either way?

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Answer 1

Example 1A is the correct one. QSYS synchronizes reset deassert internally for the Nios logic. But you need a reset synchronizer for the other logic implemented in the FPGA (outside QSYS).