Dividing multi-bit port into inputs for 2 gates

Question

I am designing a circuit where I am required to connect 32 1-bit outputs from 32 NAND gates to the input of 2 16-input OR gates. I am writing Verilog for this but unable to work out how to connect the initial 16([15:0]) bits to the input of the first OR16 and the remaining 16 ([31:16]) bits to the input of the second OR gate.

I tried this:

  or16_new o1(.orin1(xpow[15:0]), .or1out(or1w));
  or16_new o2(.orin1(xpow[31:16]), .or1out(or2w));

//where orin1 is 32 bit input to the OR16 and xpow is 32 bit wire connected to the output of 32 NAND gates. or1w and or2w are wires again, connected to the output of the 2 OR16 gates.

Compiling this returns no error in ModelSim but when using icarus, it returns the following warning -

*Port 1(orin1) of or16_new expects 32 bits, got 16. Padding 16 high bits of the port.*

And similarly for the second instance too.

So I tried

or16_new o1(.orin1[15:0](xpow[15:0]), .or1out(or1w));
or16_new o2(.orin1[31:16](xpow[31:16]), .or1out(or2w));

This returns an error, both, in ModelSim and in Icarus.

If it helps, this is how I have defined the or16_new module:

module or16_new (

input [31:0] orin1,
output or1out);

wire w9, w10, w11, w12;

nor nr_1(w9, orin1[0], orin1[1], orin1[2], orin1[3]);
nor nr_2(w10, orin1[4], orin1[5], orin1[6], orin1[7]); 
nor nr_3(w11, orin1[8], orin1[9], orin1[10], orin1[11]);
nor nr_4(w12, orin1[12], orin1[13], orin1[14], orin1[15]);
nand (or1out,w9,w10,w11,w12);
endmodule

Answer 1

You need to define the or16_new input port as

input [15:0] orin1,

Then your first try should work.