GMAC/EMAC are hardware implementations of the ethernet MAC OSI layer, usually included within SoC chips, as an embedded peripheral.
And, indeed, there is a standard hardware connection between the MAC and the PHY (usually provided by an external chip). It is called MII (Media-Independant Interface). There is also GMII for gigabit ethernet, and there are variations of both these interfaces with reduced pin counts (RMII and RGMII).
These standard interfaces define the way packet data is sent to/from MAC and PHY. Data is sent 4 bits at a time at 25MHz with MII, 2 bits at a time at 50MHz with RMII (using DDR). I don't recall how it's sent for gigabit ethernet, but you can find this info easily. There are a few control lines as well, and an additional serial link (data+clock) for configuration data. All the signals required to accomplish this are clearly described by the standard. There are 18 signals for MII and 9 for RMII. But all these signals are not compliant with anything else (it doesn't look like UART or SPI). Basically, this all allows MAC and PHY chips to be chosen in a vendor-independant way.
So, to answer you questions:
- Yes, there are dedicated pins on the CPU for this (either MII or RMII, or sometimes both, with multiplexing).
- Compared to providing ethernet through a USB peripheral, it allows dedicated bandwidth, and it doesn't take up one USB interface (leaving it available for other uses, like an external port).