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Background

I'm trying to understand if there is a dedicated protocol that dictates the way CPU on an embedded board is connected to an Ethernet chip. For example if it's some dedicated equivalent to ONFi for interfacing a NAND ic or is it a more generic protocol like SPI

This study got led me to find references to GMAC/EMAC but have so far failed to understand what does it define.

  • Would a cpu and an Ethernet chip have dedicated GMAC/EMAC pins or does it represent a protocol interface (which goes over say UART)?
  • What benefits does it bring over providing Ethernet through a USB dongle (if price isn't the issue). Would it put less load to the CPU?
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2 Answers 2

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GMAC/EMAC are hardware implementations of the ethernet MAC OSI layer, usually included within SoC chips, as an embedded peripheral.

And, indeed, there is a standard hardware connection between the MAC and the PHY (usually provided by an external chip). It is called MII (Media-Independant Interface). There is also GMII for gigabit ethernet, and there are variations of both these interfaces with reduced pin counts (RMII and RGMII).

These standard interfaces define the way packet data is sent to/from MAC and PHY. Data is sent 4 bits at a time at 25MHz with MII, 2 bits at a time at 50MHz with RMII (using DDR). I don't recall how it's sent for gigabit ethernet, but you can find this info easily. There are a few control lines as well, and an additional serial link (data+clock) for configuration data. All the signals required to accomplish this are clearly described by the standard. There are 18 signals for MII and 9 for RMII. But all these signals are not compliant with anything else (it doesn't look like UART or SPI). Basically, this all allows MAC and PHY chips to be chosen in a vendor-independant way.

So, to answer you questions:

  • Yes, there are dedicated pins on the CPU for this (either MII or RMII, or sometimes both, with multiplexing).
  • Compared to providing ethernet through a USB peripheral, it allows dedicated bandwidth, and it doesn't take up one USB interface (leaving it available for other uses, like an external port).
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  • \$\begingroup\$ So the GMAC and EMAC are software implementation of the MAC OSI layer? Am extending the comparison with USB for differences regarding the CPU usage. \$\endgroup\$ Nov 15, 2016 at 11:02
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    \$\begingroup\$ They are actually hardware implementation of the MAC OSI layer, usually included within the CPU, as an embedded peripheral. Regarding CPU usage, I think using "MII/RMII interface + PHY chip" instead of "USB interface + USB ethernet MAC+PHY chip" is more efficient, because you don't have the USB protocol overhead. \$\endgroup\$
    – dim
    Nov 15, 2016 at 11:08
  • \$\begingroup\$ Thanks, that's what I'm trying to weight out. If the USB overhead is worth the modularity it provides :) Can you please extend the answer with the info from the last comment hardware implementation of the MAC OSI layer that addresses what GMAC and EMAC are and I'll accept the answer \$\endgroup\$ Nov 15, 2016 at 11:18
  • \$\begingroup\$ You're right, this was missing from my answer. Post updated. However, I suggest you wait a bit more before accepting, you might get better answers. \$\endgroup\$
    – dim
    Nov 15, 2016 at 12:19
  • \$\begingroup\$ allows dedicated bandwidth by this you mean there isn't a bus that is shared as in the USB case? \$\endgroup\$ Nov 15, 2016 at 15:00
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GMAC is Galois Message Authentication Code (GMAC). Galois Message Authentication Code (GMAC) is an authentication-only variant of the GCM. It can form an incremental message authentication code and accepts initialization vectors of arbitrary length. The Galois mode of authentication uses the function GHASH H(A,C), which uses multiplications in GF(2128) that can easily be parallelized. The 128-bit authentication tag is defined as Tag = E K(N)GHASH H(A,C), where K is the encryption key, N is the nonce, H = E.

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