What is the difference between DCM and PLL in e.g. Xilinx FPGA?

Question

Some FPGAs have both DCM (Digital Clock Manager) and PLL (Phase Lock Loop) for use in internal clock generation.

Xilinx Spartan-6 FPGA Clocking Resources UG382 (v1.10) documentation describes a number of features for DCM:

• Eliminate clock skew
• Phase shift a clock signal
• Multiply or divide an incoming clock frequency or synthesize a completely new
• Condition a clock, ensuring a clean output clock with a 50% duty cycle
• Mirror, forward, or rebuffer a clock signal
• Clock input jitter filtering
• Free-running oscillator
• Spread-spectrum clock generation

However, to my understanding all these (or at least the majority, maybe not the "Free-running oscillator") are also available when using a PLL.

So, what is the difference in using a DCM vs. a PLL in an FPGA design?

Answer 1

Xilinx use the term DCM for their enhancement to what they used to call a DLL, or Delay Locked Loop.

This (DLL) was a tapped delay line fed from the original clock signal, by selecting different taps, you could get different delays on the output clock signal. As the delays are unpredictable, logic compared the outputs from different taps until it found which tap number gave a full clock cycle delay - it was "unlocked" until it found the right tap. Then it updated that tap number as the delays drifted (e.g. as the input frequency changed or the chip warmed up) then other delays (e.g. 90 degrees, 180 degrees, were computed from that.

So it provided vaguely PLL-like behaviour without any analog circuitry, which was difficult to achieve in their processes at the time. Downside was that the jitter spectrum was different from a PLL as the delay was always an integral number of taps.

If you cascaded DLLs or DCMs, the second one will probably work, but a third one may have dificulty locking up due to the jitter imposed by the others.

The DCM is based on the same idea but provides other functionality such as clock frequency multiplication.

Newer FPGAs offer both DCM (DLL) and PLL but I expect the DCM is still easier to produce.

Answer 2

So, first of all, how an FPGA manufacturer decides to name components is mainly a marketing choice. So there's no inherent significance in that. It's always good to remember.

Then: a PLL is really just that, a control loop in which the observed/corrected quantity is the phase (or a derivative of that) of a signal. Thus, it's a part of something that might generate clocks, but not the complete clock generator. Of course, it's like "transistor" used to stand for small radio receivers in the 1960's and 70's, because the central component was a transistor. But a transistor alone doesn't make a radio receiver.

So, whatever is called PLL in your design needs to come with a description of what it actually does. Compare that description to the description of what a DCM does. That's the best answer we can give – "PLL", again, just actually means a single control loop, not a clock generator.