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Say I have to couple a NOR \$I^2L\$ and an ECL logic circuit, in such a way that the output voltages of the \$I^2L\$ are suitable for ECL use. Let me show you what I mean: enter image description here I thought adding a voltage divider might do the trick. When we have either A or B high the output of the \$I^2L\$ is 0.2V, the collector-emitter saturation voltage. Using a voltage divider as shown in the image, I can convert this logic zero of 0,2 V to a logic zero of let's say -1,7V( less than Vref) which is the input for the ecl circuit, and will be a logic 0 in terms of the voltages present in the ecl. However, I am not sure how to make a logic 1 using this divider. The first cicruit gives us a logic 1 if both A and B are zero, and in that case the input for the second circuit is just -Vee, a logic zero, not a logic 1. Note that this is just for academical purposes, so I guess there are solutions which are easily grasped.

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  • \$\begingroup\$ 1. I don't know I2L, but it looks like it would need a pull-up resistor to produce a positive output voltage. 2. Is there a reason you can't run your ECL logic as PECL (power it from +5 and 0 instead of 0 and -5 V)? Or power your I2L from 0 and -5? \$\endgroup\$
    – The Photon
    Commented Nov 26, 2016 at 20:45
  • \$\begingroup\$ I guess we could do that, but this is the way we should approach the problem. I will try something with the pull up resistor \$\endgroup\$ Commented Nov 26, 2016 at 20:55
  • \$\begingroup\$ The circuit you have now will result in the output BJTs of the I2L gate going into reverse active operation. Maybe only when the input is high, maybe for either input state. It doesn't look like a good way to get consistent results. \$\endgroup\$
    – The Photon
    Commented Nov 26, 2016 at 20:56

1 Answer 1

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Maybe use a common-base transistor to buffer current between the positive logic circuit and negative logic circuit, something like this:

schematic

simulate this circuit – Schematic created using CircuitLab

It's up to you to find the resistor values that give proper NECL levels at the output. You don't have to be precise, ECL is pretty robust to varying logic levels if you're not trying to get maximum speed from it.

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