synthesizable reg assignment + other questions

Question

I'm at the beginning of learning verilog and some things are unclear. Also, I'm just looking for synthesizable code.

1. What are the differences between this types of assignation: Which of them is synthesizable?

    reg [3:0] data_reg = 4'b1; // what kind of assignment is this? blocking, non blocking?
   
    vs
   
    reg [3:0]data_reg;
    initial data_reg = 4'b1;  
   
    vs
   
    reg [3:0]data_reg;
    initial data_reg <= 4'b1;
   

2. Can I assign reg value to a wire, like:

   module foo (output wire [3:0] led); 
   reg [3:0] data_reg = 4'b1; 
   assign led = data_reg; 
   endmodule 
   

For the code above I get the following error: ERROR:NgdBuild:604 in ALTIUM and in XILINX ISE I get Using initial value of led since it is never assigned.

Answer 1

In verilog, reg does not represent synthesisable storage, it is more of a software construct in the language - its also used in case statements.

If you want an actual flip-flop, you need to follow this pattern:

always @(posedge clk or negedge reset_n)
if(!reset_n)
data_reg <= 4'b0000;
else data_reg <= data_input;

and, yes, you can assign any wire (output or not) from a reg (combinatorial or sequential).

Wherever you have initial, it is very likely you have something which is not synthesisable. Silicon has no concept of when initial should occur, so with initial you are maybe anticipating an earlier operation (like writing an image to FLASH memory), or relying on an FPGA synthesis flow inserting some reset initialisation for you.

Answer 2

Answer to the first question:

Blocking and Non-Blocking assignments only work in behavioral modeling. Remember the initial block is not synthesizable.

Non-Blocking:

reg X, y, z;
reg [15:0] reg-a, reg-b;
integer count;
//All behavioral statements must be inside an initial or always bloc1
initial
begin
    x = 0; y = 1; z = 1; //Scalar assignments
    count = 0; //Assignment to integer variables
    rega = 16'bO; regb = rega; //Initialize vectors
    rega[2] <= #l5 l'bl; //Bit select assignment with delay
    regb[15: 13]  <= #l0 {x, y, z) ; //Assign result of concatenation
                                     //to part select of a vector
    count <= count + 1; //Assignment to an integer (increment)
end

  In this example the statements x = 0 through regb = rega are executed
  sequentially at time 0.
  Then, the three nonblocking assignments are processed at the same simulation time.
  1. rega[2] = 1'b1 is scheduled to execute after 15units (i.e., time = 15)
  2. regb[15:13]= {x, y, z} is scheduled to execute after 10 time units 
    (i.e., time = 10)

  3. count = count + 1 is scheduled to be executed without any delay(i.e.,   time = 0)

Blocking:

initial
begin
     x = O ; y = l ; z = 1; //Scalar assignments
     count = 0; //Assignment to integer variables
     rega = 16'bO; regb = rega; //initialize vectors
     #l5 rega[2] = 1'b0; //Bit select assignment with delay
     #l0 regb[15:13] = { x , y, z) //Assign result of concatenation to
                                    // part select of a vector
     count = count + 1; //Assignment to an integer (increment)
end

In , the statement y = 1 is executed only after X = 0 is executed.    
 The behavior in a particular block is sequential in a begin-end block if   blocking
 statements are used, because the statements can execute only in sequence.     The
 statement count = count + 1 is executed last. The simulation times at which the
 statements are executed are as follows:
 1. All statements X = 0 through regb = rega are executed at time 0
 2. Statement rega[2] = 0 at time = 15
 3. Statement regb[15:13] = {x, y, zl at time = 25
 4. Statement count = count + 1 at time = 25
   Since there is a delay of 15and 10 in the preceding statements, count = count
 + 1 will be executed at time = 25 units

Here you can find which Verilog constructs are synthesizable and which are not.

http://corevlsi.blogspot.in/2014/09/verilog-synthesizable-and-non.html

Answer to the second question:

YES you can assign reg value to wire type, but in your code the synthesizer doesn't find any input to the logic and this line reg [3:0] data_reg = 4'b1; is like using initial which is not recognized by the synthesizer. So, you have to modify your code to this:

module foo (input [3:0]a, output wire [3:0] led); 
   reg [3:0] data_reg; 
   always@(a)
        data_reg = a;
   assign led = data_reg; 
endmodule