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I'm contemplating a non-electronic system that is analogous to a D flip-flop being fed an analog signal and a fixed-frequency clock. The system has an analog input which changes over time. The output of the system is a single bit. The analog input is sampled at fixed intervals. The output goes high if the input exceeds one value, and goes low if the input deceeds a lower value.

I feel like this circuit has a name or common application, but I can't track down what it might be.

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    \$\begingroup\$ Schmitt trigger , normally inverter output 1/3 to 2/3Vcc thresholds. 'HC14 \$\endgroup\$
    – D.A.S.
    Commented Feb 3, 2017 at 3:55
  • \$\begingroup\$ but this not the same as a D FF, it is just a hysteretic input. \$\endgroup\$
    – D.A.S.
    Commented Feb 3, 2017 at 4:09
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    \$\begingroup\$ i think a D flip-flop does have hysteresis. that positive feedback is how it remembers its state. so i think your first comment is correct. \$\endgroup\$ Commented Feb 3, 2017 at 4:46
  • \$\begingroup\$ This is called a clocked comparator. It could be implemented with a Schmitt trigger on the D input, but most usually with a comparator. You would use it where you interface into a larger synchronous system with fixed timing domains. \$\endgroup\$ Commented Feb 3, 2017 at 5:32
  • \$\begingroup\$ Another name is latched comparator. The hysteresis is not a standard feature, but easily added with a feedback resistor. \$\endgroup\$
    – The Photon
    Commented Feb 3, 2017 at 6:06

3 Answers 3

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If the output bit stream is low-pass-filtered and fed back and subtracted from the analog input, you have a first-order delta-sigma tracking converter.

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  • \$\begingroup\$ Fascinating idea! \$\endgroup\$ Commented Feb 5, 2017 at 3:34
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The output goes high if the input exceeds one value, and goes low if the input deceeds a lower value.

That sentence describes a Schmitt trigger: -

enter image description here

Top signal is the input. Middle single is a normal comparator output. Bottom signal is the Schmitt trigger output - notice how it switches high when the analogue input passes the high trigger threshold and only returns to a low output when the analogue input falls below the low trigger input value.

The analog input is sampled at fixed intervals.

That implies a sample and hold circuit: -

enter image description here

It sounds like you are describing a schmitt trigger being fed from the output of a sample and hold circuit that, in turn, is fed from the analogue input.

The output of the system is a single bit.

Yes it is, agreed.

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It's an A/D converter, of course. Whatever the D threshold is, at clock time the Q and /Q outputs very quickly settle on a digital representation of the one-bit digitization of the input value (0 for under-threshold, 1 for over-threshold).

A high-resolution digitization, it isn't. But, the captured value is sampled at a very precise time.

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  • \$\begingroup\$ it's a Schmitt trigger. \$\endgroup\$ Commented Feb 3, 2017 at 4:47
  • \$\begingroup\$ If there are two thresholds, that's not a D input to a flip/flop. And, if there's a master clock, it's not a Schmitt trigger. Maybe a Schmitt trigger with a latch? \$\endgroup\$
    – Whit3rd
    Commented Feb 3, 2017 at 4:52
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    \$\begingroup\$ any gate has a different OFF threshold than ON threshold. and the difference between the two thresholds is called the "noise margin". (oops. i got that terminology wrong, the noise margin is the difference of the output voltage range and input range for each logic state.) i guess you can call it a clocked Schmitt trigger. \$\endgroup\$ Commented Feb 3, 2017 at 5:03
  • \$\begingroup\$ If the signal were DC coupled, it might have margins, but AC coupling happens, too. The size of the Schmitt deadband might mean that the A/D conversion just rounds off toward a no-change. \$\endgroup\$
    – Whit3rd
    Commented Feb 3, 2017 at 5:10

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