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I wanted to use the Square-Root Operation of the FPU (6.1) in the Xilinx's Logic Core IP. I don't know what latency should I choose. Can someone help me with that?

By default it chooses the maximum possible latency. Why would anyone want to choose the maximum possible latency?

I will be using it on a Xilinx Virtex-6

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Higher latency generally makes for smaller logic as it allows iterative approaches to calculating your square root.

In general choose the highest latency your process can cope with, low latency floating point is Expensive in terms of area and speed (High latency floating point is just small 'e' expensive.

Avoid FP if at all possible, most modern FPGAs have large numbers of fairly wide hardware integer multipliers that can do fixed point just fine, floating point not so much.

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  • \$\begingroup\$ But can any FPGA (with available resources) implement any latency operation? Also, can I know how many LUTs or DSPs will an implementation use? \$\endgroup\$ Mar 5, 2017 at 3:23
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    \$\begingroup\$ The floating point core you are using should have a manual that will give you all the details of the trade offs, including resource usage. \$\endgroup\$
    – Dan Mills
    Mar 5, 2017 at 3:37
  • \$\begingroup\$ Higher latency in clock cycles will usually also allow a higher clock frequency. \$\endgroup\$ Mar 6, 2017 at 23:55

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