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The 8086 microprocessor can address up to 1MB of memory (20 bit address bus). Most books show a diagram of this 1MB memory which in turn shows interrupt vector tables, DOS function, BIOS routines taking up memory space etc

MY QUESTION:

When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. Is the ROM + RAM = 1MB of memory interfaced? If yes, when memory mapped I/O is shown as a memory segment in this 1MB memory space.....do they mean that the I/O ports is taking some of the RAM memory?

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  • \$\begingroup\$ Here's a PDF source that is a small extraction from Edward Solari's book, "ISA & EISA Theory and Operation:" ee.nmt.edu/~rison/ee352_spr12/PC104timing.pdf It might help to read the timing diagrams. \$\endgroup\$
    – jonk
    Commented May 9, 2017 at 7:01

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When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. Is the ROM + RAM = 1MB of memory interfaced?

Correct. The CPU does not distinguish between RAM and ROM; the 1 MB address space is shared between both.

If yes, when memory mapped I/O is shown as a memory segment in this 1MB memory space.....do they mean that the I/O ports is taking some of the RAM memory?

Sort of. I/O ports (as used by the IN and OUT instructions) are technically a separate address space on x86, and do not occupy memory address space.

Memory-mapped peripherals, however, are accessed like memory, and occupy memory address space (which they share with RAM and ROM).

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  • \$\begingroup\$ 1. "I/O ports are technically a separate thing on x86, and do not occupy address space " - could you please elaborate a little? 2. "which they share with RAM and ROM"- If an I/0 port takes up address space....then it is therefore taking up space INSIDE the RAM right? \$\endgroup\$
    – Eliza
    Commented May 9, 2017 at 5:47
  • \$\begingroup\$ You use the CE line to talk to one or the other, as far as I remember when I wire wrapped an 8088 \$\endgroup\$
    – Voltage Spike ♦
    Commented May 9, 2017 at 6:34
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    \$\begingroup\$ @eliza I used to wire-wrap up ISA boards -- still wish I could, as the PCI bus takes VERY EXPENSIVE equipment and design time whereas the ISA bus is CHEAP and EASY for anyone. The 8086 has 6 basic bus cycle types: (1) instruction read, (2) memory read, (3) memory write, (4) I/O read, (5) I/O write, and (6) interrupt acknowledge. [There is also a line so that the I/O cycles can be either 8-bit (6 cycle) or 16-bit (3 cycle.)] Since devices on the bus can tell the difference, the I/O is in a different address space than RAM/ROM. (There is also a (7) halt-cycle.) Find Edward Solari's book. \$\endgroup\$
    – jonk
    Commented May 9, 2017 at 6:42
  • \$\begingroup\$ @Eliza "I/O ports" are a separate thing with a separate (16-bit) address space, but if a device does MMIO (most newer devices do, and even in the old days something like a video card is going to map VRAM into memory pace) then that happens in memory address space. Most of the upper 384k is given over to such purposes. \$\endgroup\$
    – hobbs
    Commented May 9, 2017 at 17:06
  • \$\begingroup\$ I/O operations use the same address and data lines as memory operations, but other signals on the bus distinguish I/O access from memory access. No correctly implemented memory device will respond to an I/O access at address F00, and no I/O device will respond to a memory access at the same address. \$\endgroup\$
    – Solomon Slow
    Commented May 9, 2017 at 18:09
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First, download 8086 datasheet for reference.

When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer.

They refer to the addressable space of the microprocessor. Look into datasheet, it shows A19:A16 and AD15:AD0 lines which are used for addressing outer space during T1 cycle. CPU does not care what is there in the outer space, it just tells there that it wants contents of the specific address.

Is the ROM + RAM = 1MB of memory interfaced?

You can have ROM, RAM and anything responding on the data bus to the CPU when it requests specific address. ROM and RAM are just most common types of devices which will respond.

when memory mapped I/O is shown as a memory segment in this 1MB memory space

Look here. CPU uses one pin to identify to its outer world type of command it uses for access (read [RD] or write [WR]), its name is M/IO. If this pin is high, command CPU executing is MOV instruction, and contents are expected from memory space. When this pin is low, CPU is executing IN/OUT instruction, and contents are expected from input/output device.

However, nothing prohibits the would-be I/O device to respond when this M/IO pin is high, and be like a memory.

In general, these types - memory space and I/O space were designed in the old good days when RAM was scarce and logic was expensive; having separate I/O circuitry will free up memory addressable space, and was smaller than memory addressable space (e.g. 16 bit, or even 8 bit instead of 20/16 bit). It was convenient and understandable.

However some designers of the devices decided that they would want their would-be I/O devices to respond to RAM cell reads and writes, rather than to port read/writes - the reasons could be that RAM I/O is faster, takes up less instruction bytes etc.

do they mean that the I/O ports is taking some of the RAM memory?

Yes - memory mapped I/O device, responding to the read/write request in memory addressable space, takes that space out of RAM useful space. For example, in older 8-bit computers with slotted RAM designers often implemented floppy disk controller I/O (which is input/output rather than memory device) registers to be addressable through special RAM locations.

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    \$\begingroup\$ Quite a good answer, except the last part: no, on 8086, the I/O ports do NOT take up RAM space. \$\endgroup\$
    – glglgl
    Commented May 9, 2017 at 9:45
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    \$\begingroup\$ Agreed, this part was confusing, edited adding "memory mapped". Previous question was containing "memory mapped I/O" and I assumed that it relates to this last question too. Now should be 100% clear. \$\endgroup\$
    – Anonymous
    Commented May 9, 2017 at 11:42

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