Set array of wires to integer value in Verilog test bench

Question

I am writing a test bench for a module that takes an array of inputs that represents a number using the following code:

module ComparatorTest;
wire [3:0] a;
wire [3:0] b;
output aHigher, bHigher, equal;

Comparator c (a, b, aHigher, bHigher, equal);

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, ComparatorTest);

    # 0  a[3:0]=1111, b[3:0]=0000;
    # 20 a[3:0]=1111, b[3:0]=1111;
    # 40 a[3:0]=0000, b[3:0]=1111;
    # 60 $stop;
end
endmodule

I want to be able to set the arrays a and b either in base 10 or in binary like I would a number. How do I go about doing this? The code that I have gives me a syntax error (ComparatorTest.v:12: Syntax in assignment statement l-value.)

Answer 1

Change wire to reg and you should be good to go.

And if you want to set them in binary, then you have to prefix with 4'b, like so: 4'b0000, 4'b1111, etc. The 4 indicates the number of bits. If you want decimal, then do 4'd0, 4'd15, etc.