I'm designing a interface PCB with I/O modules using ethernet. It is my first PCB with high speed communication, which is giving me a lot of worries.
In the modules documentation it says that the LVDS differential impedance shall be 100ohm, but no tolerance. It also recommend that they are routed between two ground planes.
I have read design guides and rules:
My PCB stacking design looks like this:
- 18um copper
- 0.36mm FR-4 STD
- 35um copper
- 0.71 FR-4 STD
- 35um copper
- 0.36mm FR-4 STD
- 18um copper
Questions
I'm routing on the second copper layer, which makes the distance to the upper and under GND layer different is that a bad idea?
The guides says spacing under 0.25mm between the differential pair with a width of 0.25mm trace. when i use Saturn PCB design to match the differential impedance to 100ohms i get 0.6mm spacing with a trace width of 0.254mm. This is more than the to times trace width which is recommended (also read as close as possibly). Should i make the trace width smaller or change something else?
I read that the maximum trace length should be 50mm(TIA/EIA-644 LVDS), which is not er problem. But what about the length differences tolerance ?