We are having a lot of difficulties sharing a uSD card between two devices (an Atmel micro which uses the SPI, and a camera). We used to do this using relays, and all worked fine, but cards got faster and faster and now we are getting a lot of failures.
We have therefore been evaluating using digital multiplexers. We initially tried the FSSD07 Fairchild mux but had problems when the uSD was being switched down from 3.3 V to 1.8 V operation as the data and clock lines change voltage, but not the supply rail. This messed up the high and low level thresholds.
Then we made up a PCB to try using the TI TS3A27518E mux. Things were definitely better but we are still having problems with bus speeds over 50MHz. All of the SD lines apart from VDD and VSS pass through this one Mux (6 channel). VDD is switched separately. Looking at the signals on the oscilloscope, the clock sometimes begins to look nasty at the higher speeds. Looks like we may be having two issues:
There could be some stray capacitance causing rolling of the clock signal edges which at the higher speed is delaying the rise and fall times enough that the clock is changing state before reaching the correct logic levels (this presents itself on the oscilloscope as a smaller amplitude clock with a DC offset).
The PCB is about 80 mm x 24 mm, 4 layer (top, gnd, pwr, bottom) and tracks are 0.5 mm where possible, or else 0.3mm wide. PCB track resistances are less than 80 mΩ so that shouldn't be a problem. The mux resistance is 300 mΩ and given that I at times see a time constant of 10 ns, that would equate to about 5 nF stray capacitance. Capacitance of the switch is supposed to be about 21 pF. I would have thought 5nF is way too big for stray capacitance.
Secondly, sometimes the clock looks like it is getting some reflection interference (admittedly I didn't specifically impedance match my PCB tracks).
Not really too sure if I am approaching this all the right way as I don't know a lot about the SD requirements. At first I thought the DC offset on the CLK was causing all the issues but then there are times where I see a DC offset and yet the camera writes to the card without any issues.
We would like this to work with a variety of cameras that can handle the higher speeds. We find that Nikon cameras have the most errors, while Canon and Fuji cameras seem to do a lot better. We really need to be confident that we will have zero interface errors. Any thoughts on what I can try to get the SD working at 100 MHz CLK speeds?
Limited to how many pics I can insert, so here is a screenshot showing the PCB layers and the important half of the schematic.
This second pic shows in the top LHS the point where SD comms fails (when it switches to the higher speed). Below that are pics of the PCB where I bypassed the switch with 10 Ω resistors and then also with wire links. On the RHS is the CLK signal (Ch 3) when connected to the Nikon D5300 (comms failed). Ch 1 is the same CLK at the input (connected to J5). From that it makes me think that the camera is sinking the clock signal at the uSD. CLK voltage is bigger in magnitude than the J5 side.
The problem is exacerbated when we use a SD card extender between the camera and my PCB. We could work around this by having the board in the camera and then running a cable between our micro and this board but that makes things a bit messier.
If I can't sort out a hardware solution, is it possible to write from the micro to the SD cards to force them to operate at a slower speed when the uSD connects to the camera?
Looking forward to seeing what wealth of info I might get back:)
