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enter image description here

For the above typical circuit, when the transistor is off many texts show the current directions as shown in pink colour. I also know from basic circuit theory: "The algebraic sum of all currents entering and exiting a node must equal zero"

During the transient when the transistor is off let's stop the time and check the nodes.

I look at node m and node n and try to apply KCL:

at node m Id = I_L

at node n Id = I_L + I_x

which results as Id ≠ Id

Where am I wrong here?

(Is this phenomena similar to this situation?)

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    \$\begingroup\$ Unless I_x is 0. \$\endgroup\$
    – Ignacio Vazquez-Abrams
    Commented Oct 20, 2017 at 1:23
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    \$\begingroup\$ Um. \$I_x=0\$. So all is good. \$\endgroup\$
    – jonk
    Commented Oct 20, 2017 at 1:23
  • \$\begingroup\$ @jonk If Ix = 0, then Id = I_L at any moment when the transistor is off. But Id and I_L are different in simulations and Ix is not zero. Have you tried simulating this? \$\endgroup\$
    – user16307
    Commented Oct 20, 2017 at 1:34
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    \$\begingroup\$ @user16307 How would you want me to simulate this, exactly? Care to provide a full schematic to try out? In any case, it all works out just fine and KCL is always working fine. The universe would explode if currents accumulated. So there is no worry. Sometimes, you have to be aware of parasitics (if simulating) and also alternate pathways. But the current sums all work out. \$\endgroup\$
    – jonk
    Commented Oct 20, 2017 at 1:37
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    \$\begingroup\$ @ThePhoton I think you are right. There is an interval during transition(from on to off for the transistor) where the sum of drain current and diode current is equal to inductor current; after that the drain current goes to zero and the diode current settles to the same as resistor current. I neglected the effect of the FET's discharge, that was the mistake. \$\endgroup\$
    – user16307
    Commented Oct 20, 2017 at 2:12

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There should be no I_x current as both node n and the positive terminal of your source are at the same potential.

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  • \$\begingroup\$ Input to transistor gate is a high freq. pulse. And during this operation at any moment when the transistor is off Id and I_L are different in simulations and Ix is not zero. \$\endgroup\$
    – user16307
    Commented Oct 20, 2017 at 1:37
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    \$\begingroup\$ @user16307 if I_x is not zero, neither is the current through your “off” transistor. \$\endgroup\$
    – Edgar Brown
    Commented Feb 11, 2019 at 16:17
  • \$\begingroup\$ There is zero resistance between the positive source terminal and node n so they are, in effect, the same. I_x is the current delivered by the source. \$\endgroup\$
    – Finbarr
    Commented Jun 13, 2019 at 12:31

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