FPGA: count up or count down?

Question

I am learning to use an FPGA (Papilio development board,which has a xilinx spartan3e, using vhdl).

I need to divide an incoming pulse by a (hard coded) number.

I can see 3 options - roughly, as pseudocode (using 10 counts as an example):

1. Initialize to 0, on input rising edge increase by 1, compare to 10; if they are equal, reset to 0 and trigger output pulse
2. Initialize to 10, on input rising edge decrease by 1, compare to 0; if they are equal, reset to 10 and trigger output pulse
3. Initialize to 9, but make sure there is at least 1 leading "0" bit, which is my output bit. On input rising edge decrease by 1. On rising edge of the output bit, reset.

The duty cycle is unimportant.

Is one of these better than the others? Is there an even better method that I haven't thought of?

Is there a "standard" way that will give the compiler the best chance of optimizing?

Answer 1

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed.

Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going between the counters so that it can signal that the target number has been reached. Option 2 may be slightly faster than 1, since it all can be straight OR'd together without any inverters, but again you run into small technology differences where it may be faster to AND or XOR.

Option 3 skips the comparison for the low cost of one extra bit in the counter. This should be worth it, unless you are severely restricted in flip-flops.

One fun fact about counters is that they tend to be grouped into a device specific size within a logic block, and you will see the timing change more than expected if this extra bit pushes you out of that group.

Answer 2

One other option would be to initialize the counter to 6 (=2⁴ - 10), count up, and then reset when the carry output activates (i.e., the FFs are all ones).

The advantage of this is that it doesn't require an extra FF, and many FGPAs have dedicated auxiliary logic to speed up this kind of carry operation in a counter or adder circuit.

Answer 3

Depends. For example: flip-flop propagation delay for 0→1 and 1→0 can be different, and hence a counter's transition delays for 000→001 and 001→000 can be slightly different. It may be higher or lower, depending on the cmos technology used in FPGA. So you have to synthesize and find out which one has better timing performance.

Answer 4

From a compiler writer's perspective: if you use integer, the internal representation is undefined, and the compiler is free to choose the most efficient implementation.

If you force a particular internal representation, the optimizer will still attempt to improve it, but it will start from a slightly worse vantage point.

Some FPGAs have "preload" capabilities, where registers can be initialized to arbitrary values, in which case initializing to \$N-1\$, counting down and using the topmost carry bit as output and reset (in the next cycle) is more efficient than implementing both an adder and a comparator. Without preload, an adder might be better.

Unless you know the internal structure, the resources allocated to other logic (many FPGAs have dedicated floating point multiply-add logic that you can also use to implement a counter if you have leftover units) and are entirely sure that you won't be switching to a different model, the answer is "don't think about it".