How do I access the PCM flash ram on a Nexys3 FPGA board?
I've got a simple T80 (Z80) CPU core project working with a Core Generator ROM module, but not having any luck with the flash ram. The Nexys 3 Reference Manual suggests using the Reference Designs from the Digilent website, but there isn't actually one for the Nexys 3 board - I've asked Digilent and they say there's only one for the Nexys 2, which I've been through. I've also read most of the data sheet for the flash chip - Micron NP8P128A13T1760E but can't get it working.
So I've put together the most minimal project I can think of: a simple state machine that attempts to read the first word from the flash ram and display the lower byte on the 8 leds on the board. See the VHDL below. I'm loading up the flash ram using the Adept memory utility, but all I ever seem to get its 0xFF displayed.
(Update, I've just found that if I press the button I've got wired to reset it displays 0x06, but that's not what's been put into flash)
My understanding of how it should work is:
- Set FlashRP = 1, FlashCS = 1, MemOE = 1, MemWR = 1,
- Set address to MemAdr (I've hard coded to 0)
- Enable flash - FlashCS = 0
- Enable out - FlashOE = 0
- Read from MemDB
My test project runs these steps on a 3.375Mhz clock (since that's what the T80 will run at).
One thing I'm not sure about is the Nexys3 Reference Manual refers to some other signals that are common to the RAM and the Flash - namely CLK, ADV and WAIT - but I've not been able to correlate these to the data sheet for the flash chip.
What am I missing?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Top is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0);
MemOE : out STD_LOGIC;
MemWR : out STD_LOGIC;
FlashCS : out STD_LOGIC;
FlashRP : out STD_LOGIC;
MemAdr : out STD_LOGIC_VECTOR(26 downto 1);
MemDB : inout STD_LOGIC_VECTOR(15 downto 0)
);
end Top;
architecture Behavioral of Top is
signal slow_clock : STD_LOGIC;
signal led_reg : STD_LOGIC_VECTOR(7 downto 0);
signal state : unsigned(3 downto 0) := "0000";
signal state_next : unsigned(3 downto 0);
begin
led <= led_reg;
-- Clock Generation
clock_core : entity work.ClockCore
PORT MAP
(
clock => clock,
clock_3375 => slow_clock, -- 3.375 Mhz clock
RESET => reset
);
process (slow_clock, reset)
begin
if (reset='1') then
state <= "0000";
led_reg <= "00000000";
elsif (slow_clock'event and slow_clock='1') then
state <= state_next;
if (state = "1110") then
led_reg <= MemDB(7 downto 0);
end if;
end if;
end process;
MemAdr <= "00000000000000000000000000";
MemDB <= "ZZZZZZZZZZZZZZZZ";
MemWR <= '1';
FlashRP <= NOT reset;
process (state)
begin
case state is
when "0000" =>
-- initialize
FlashCS <= '1';
MemOE <= '1';
when "0001" =>
-- enable flash
FlashCS <= '0';
MemOE <= '1';
when "0010" =>
-- enable flash output
FlashCS <= '0';
MemOE <= '0';
when others =>
-- hold steady
FlashCS <= '0';
MemOE <= '0';
end case;
end process;
state_next <= "1111" when (state="1111") else state + 1;
end Behavioral;
Here's the reference material I've been using:
