Problems with DC analysis of a PMOS circuit

Question

I'm beginning with electronics and I've picked up the book from Donald. A. Neamen - Microelectronics. I'm stuck at a simple example of DC analysis for this PMOS circuit.

^{simulate this circuit – Schematic created using CircuitLab}

I have to find: $$I_D, V_{SG}, V_{SD}$$

Parameters given are: $$K_P = 120uA/V^2, V_{TP} = -0.3V$$

Correct results are:

$$V_{SG} = 1.631V, I_D = 0.2126mA, V_{SD} = 3.295V$$

This is how my calculations go:

$$V_G = (R_2/(R_1+R_2))*(V_+ - V_-)+V_- = 0.33V$$

I took the assumption that the transistor is in saturation, therefore:

$$I_D = K_P*(V_{SG}+V_{TP})^2$$

Now I used the upper right loop:

$$V_+ - V_G = R_S*I_D + V_{SG}$$

After these two equations, I used a handheld computer to solve these two equations for \$V_{SG}\$ and got two results and none of them is right...

$$V_{SG1} = -2.03V, V_{SG2} = 1.24V$$

What am I doing wrong here? The correct \$V_{SG}\$ is ~1.6V.

Thank you!

EDIT:

Here are the results from the book.

Answer 1

Something is wrong here. The range between the two supplies in 4.4V, but with a 212.6 μA current, the drop across the source and drain resistors is:

$$212.6\mathrm{\mu A} \cdot (6000\mathrm{\Omega} + 42000\mathrm{\Omega}) = 10.2\mathrm{V}$$

That's not even including \$V_{SD}\$.

Plugging your circuit into CircuitLab gives:

$$V_{SG} = 1.43\mathrm{V}, V_{SD} = 887.5\mathrm{mV}, I_D = 73.18\mathrm{\mu A}$$

which is not in saturation and is not anything close to the book's answer.

I suspect this is an error introduced when the textbook was updated for a new edition. Unfortunately, there doesn't seem to be any errata listed on the publisher's web site.

Answer 2

Your calculation for VG is correct.

The correct result for ID is not 0.2126mA.

You only have 4.4V total supply voltage. But the resistance is 48K ohms. Therefore the upper bound on the drain current is 4.4V / 48K = 91.6uA. The real answer will be a bit less than that.