what logic family does tri state logic fall into?

Question

Here is a good Wikipedia on logic families.

This seemed like a particularly important line.

Of these families, only ECL, TTL, NMOS, CMOS, and BiCMOS are currently still in widespread use.

I've been reading about tri-state logic, but I cannot seem to find the relationship to the logic families. In this article, it says the logic families of circuits need to be compatible, so I just want to make sure I don't ruin the components that I buy. See section #2.

All circuits within a logic family are compatible with other circuits within that same family because they share the same characteristics.

• How does tri-state fall into this?
• What logic family would I have if I just had a HIGH/LOW, but not Undefined (open)?

Here's another reference to tri-state logic that I was reading.

Answer 1

Tri-state belongs to all logic families, ECL, TTL, NMOS, CMOS, and BiCMOS. This type of logic is able via a control pin to cut its output drivers off.

This is important when many devices share a common data bus but only one at a time can 'drive' the bus, including the CPU/MPU and DMA controllers. The top of the CPU/MPU/DMA address map reserves a few bits to select one device at a time to read from (so the IC is taken out of tri-state briefly), or to write data to.

Obviously a CPU/MPU/DMA write to a IC has no tri-state issues, as the CPU/MPU is the current bus 'master'. The CPU/MPU is usually reading or writing data so it seldom has its bus drivers go tri-state.

An exception would be an external DMA IC transferring data from an Ethernet IC to flash or dram memory. This is usually done in 'burst' of 4 kilobytes or more so the CPU/MPU is not idle for very long.

The CPU/MPU often grants a request from another IC (such as Ethernet or video or the DMA IC) to allow external data transfers while the CPU/MPU does internal chores or just idles for a short time.

This is NOT the same as wired 'or' logic because when not in tri-state a buss buffer or data latch can drive both high (1) and low (0) logic. These buffers and latch's are part of the 'glue' logic that makes things work, and is abstracted from the software for the most part.

Answer 2

A digital output stage of two transistors in series has four possible states, only three states are usefull.

• State 1: Output low, the transistor connected to ground is conducting, the one connected to supply is isolating.

• State 2: Output high, the transistor connected to ground is isolating, the one connected to supply is conducting.

• State 3: Output neither high nor low, both transistors are isolating. The output resistance is high and the output is passive. The voltage at output may be controlled by another active output connected to the same line.

• State 4: This state is forbidden, both transistors are conducting and the resulting high current is destroying the output.

Tri state outputs may be used with bipolar or CMOS transistors independant of logic family or logic levels. They are very usefull for buses, one active output controls the bus state (high or low) and all other outputs on the bus are passive high resistance in the third state. It should be avoided that two outputs are active at the same time, one low and the other high. A high current is flowing between these two active outputs and may destroy the outputs by excess heat.