How does the Cortex M0+ processor use the AHB-Lite interface to fetch instruction and data?

Question

How does the Cortex M0+ processor use the AHB-Lite interface to fetch instructions and data? Are instruction fetches done always using NONSEQ? How does it fetch data from memory (using burst or NONSEQ transfers)?

Answer 1

From the ARM M0+ manual, revision r0p1:

AHB-Lite interface
Transactions on the AHB-Lite interface are always marked as non-sequential.