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Most microcontrollers use successive approximation for their ADCs. These charge up a sample and hold capacitor, and then use this capacitor as the basis for the successive approximation algorithm.

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I'm working on an extremely low power project, where the charge held by the capacitor starts to become significant. The question is, after the adc charges up the capacitor, does it discharge it? I assume there will be some leakage as well, but I'm curious as to whether there is an intentional discharge step. If it's sampling the same voltage repeatedly, will there be a significant (microamps) current flow?

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  • \$\begingroup\$ Sounds like a data sheet answer is needed. \$\endgroup\$
    – Andy aka
    Commented Apr 18, 2018 at 13:48
  • \$\begingroup\$ I'd say this depends on the specific implementation. If I were to design such a circuit I'd probably discharge the capacitor as it would likely be unexpected if a current was flowing out of the ADC (although it wouldn't be much) if the last voltage was higher then the current voltage. \$\endgroup\$
    – Arsenal
    Commented Apr 18, 2018 at 13:52
  • \$\begingroup\$ I sense some disconnect in the language of this question. "The ADC" doesn't "charge up the capacitor", the cap is charged by input buffer (or directly from the Vin). There is no need to discharge the cap, since it will be charged to new "sample" level from the source. And the "charge held by the capacitor" can't contribute anything to power dissipation, the power is lost when sampling a different Vin level. I guess there were dissertations written on this subject 30-40 years ago, EE articles, patents. \$\endgroup\$
    – Ale..chenski
    Commented Apr 18, 2018 at 17:45
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    \$\begingroup\$ @AliChen The point of the question is whether or not the capacitor is usually discharged by the ADC after each reading, in order to prevent possibly unexpected behaviour like Arsenal points out. If it is, then power will be lost. AFAIK, many/most MCUs charge the S/H capacitor directly from Vin, rather than using a buffer \$\endgroup\$
    – BeB00
    Commented Apr 18, 2018 at 17:59
  • \$\begingroup\$ But there could be a parasitic leakage via switches, which would lead to some effective current flow from/to Vin even when sampling the same voltage. \$\endgroup\$
    – Ale..chenski
    Commented Apr 18, 2018 at 17:59

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In general the charge on the sample-hold capacitor is driven to near-zero, using charge taken from the Vref pin.

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    \$\begingroup\$ Yup i wondered if it might be something like that, do you have a source? Do you know why they do that? \$\endgroup\$
    – BeB00
    Commented Apr 20, 2018 at 12:35
  • \$\begingroup\$ I've read papers on the SAR algorithm, using switched-cap binary-approximation method. The sampled-charge is taken into a binary-weighted array of capacitors, along with snippets of charge from the VREF input. Charges are progressively used to seek a null at input to the analog comparator, with the comparator deciding whether each bit (starting with Sign or MSB bit) is a ONE or a ZERO. At the end, the sampled-charge has been totally consumed (or driven to less than one quanta of voltage) by the binary approximation algorithm. The IC must avoid duplicating large capacitor, so no buffering. \$\endgroup\$
    – analogsystemsrf
    Commented Oct 12, 2019 at 17:40

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