Difference in the characteristic impedance of a low frequency signal

Question

In one of my PCB design, for a RS 485 signal termination resistor of 120 ohm is there. But the differential characteristics impedance of the signal is taken as 100 ohm instead of 120 and the signal travelling down the trace is of low frequency. Does this impedance mismatch/change affects the low frequency signal particularly at the destination with reflections or some other SI issues?

Answer 1

If we put in a voltage pulse Vi into a line having characteristic impedance Z0 that is terminated with impedance ZL the reflected voltage is...

$$V_R=V_I\frac{Z_L-Z_0}{Z_L+Z_0}$$

For a 100 ohm line terminated with 120 ohms the reflected voltage is...

$$V_R=V_I\frac{120-100}{120+100} = \frac{1}{11} V_i$$

This means that there will be a reflection of about 9.1% of the input signal.

I believe the RS485 spec says that the transmitter needs to output at least 1.5V and the receiver needs to detect any signals of at least 200mV. In a typical case a 9.1% reflection is not going to cause problems on RS485.

For such a small reflection to actually cause problems, the signal would have to be very attenuated by the time it reached the receiver. This could happen for example if the wires were very long (like thousands of meters).

SLOW SIGNALS

If the RS485 physical layer is used with UARTs on both ends, and the baud rate is slow we might also consider whether the signal settles before the bits are sampled.

Propagation speed in a 100 ohm cable might be like 0.6 C (so like 0.18 m/ns). If we had (for example) a 100 m cable the signal would take like 555ns to travel the length of the cable.

For 9% reflection the signal would be settled to within 99% of its final value if it bounced back and forth to the receiver twice. From the time the receiver first saw the signal it would need to make one more round-trip of 1.11us to be 99% settled.

Note that I am just picking 99% percent settled because it is an easy case involving one round trip of reflections, which allows me to demonstrate the calculation.

If the UART samples the bits at the middle of the bit-time, then we would probably be OK if the round trip was less than 1/2 bit-time (let's say 1/4 bit-time to be safe and account for oscillator mismatch).

In that case we would want the bit-time to be at least 1.11us * 4 = 4.44us.

So, in the example case of 100m of cable, baud rates below 225kbps would likely be completely settled (like to within 1% of final value) before the receiver sampled the bit.

You can do the same calculation with your own cable length to find the limiting baud rate for your application.

Answer 2

If you can afford to have a delay between sending messages on the line I would do that. As it will ensure that previous messages will have enough time to dissipate. The time needed for the signal to dissipate is depending on the length of the line so experimentation might be needed, but a bit of code can be written that tests reliability of the line with an increasing delay and you stop increasing when the message transmission is reliable.

Most lines typically range from 100Ω to 150Ω for twisted-pair cables. As long as you have resistors on both ends of the line you should be fine.

For additional reading look at this page as it explains how to deal with the reflection coefficient optimally.