Modelsim simulation doesn't work

Question

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know this is a noob question, but I am a noob so that's ok.

HERE is my entity:

Library IEEE;
use ieee.std_logic_1164.all;
-----------------------------------------
PACKAGE my_vector IS
    TYPE vector_array IS ARRAY (Natural RANGE <>) OF STD_LOGIC_VECTOR(8-1 downto 0);--(Natural RANGE <>,Natural RANGE <>) OF STD_LOGIC;
END my_vector;
-----------------------------------------
Library IEEE;
USE work.my_vector.all;  --using my package
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.NUMERIC_STD.all;
USE IEEE.STD_LOGIC_ARITH.UNSIGNED;
use ieee.NUMERIC_STD.UNSIGNED;
-----------------------------------------
Entity mux IS
   GENERIC ( M : INTEGER := 8;
             N : INTEGER := 3 );
    PORT (  a   : IN vector_array ((2**N)-1 downto 0); -- ,M-1 downto 0);
            sel : IN INTEGER;                          --STD_LOGIC_VECTOR(N-1 downto 0);
            y   : OUT STD_LOGIC_VECTOR(M-1 downto 0));
END mux;
-----------------------------------------
ARCHITECTURE logic of mux is

signal test : STD_LOGIC_VECTOR(8-1 downto 0); 
    BEGIN
    y  <= a(sel);
END logic;

---

HERE is the TESTBENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-----------------------------------------
PACKAGE my_vector IS
    TYPE vector_array IS ARRAY (Natural RANGE <>) OF STD_LOGIC_VECTOR(8-1 downto 0);--(Natural RANGE <>,Natural RANGE <>) OF STD_LOGIC;
END my_vector;
-----------------------------------------
Library IEEE;
USE work.my_vector.all;  --using my package
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.NUMERIC_STD.all;
use ieee.std_logic_arith.UNSIGNED;
-----------------------------------------
entity tb_GenericMux is
--  Port ( );
end tb_GenericMux;

----------------------------------------------------------------
architecture Behavioral of tb_GenericMux is
constant TIME_DELTA : time := 10 ns;
--DUT-----
COMPONENT Mwidth_by_Ninputs_MUX IS

   GENERIC ( M : INTEGER := 8;
             N : INTEGER := 3 );
    PORT (  a   : IN vector_array ((2**N)-1 downto 0); --,M-1 downto 0);
            sel : IN INTEGER;--STD_LOGIC_VECTOR(N-1 downto 0);
            y   : OUT STD_LOGIC_VECTOR(M-1 downto 0));
END COMPONENT;
------------
use work.my_vector.all;

signal input :  vector_array((2**3)-1 downto 0);--,8-1 downto 0);
signal slt   :  INTEGER;--STD_LOGIC_VECTOR(3-1 downto 0);
signal outp  :  STD_LOGIC_VECTOR(8-1 downto 0);

begin
--connect DUT
DUT: Mwidth_by_Ninputs_MUX port map(a   => input,
                                    sel => slt,
                                    y => outp);


PROCESS
BEGIN
input(0) <= "00000001";
input(1) <= "00000010";
input(2) <= "00000100";
input(3) <= "00001000";
input(4) <= "00010000";
input(5) <= "00100000";
input(6) <= "01000000";
input(7) <= "10000000";

slt <= 1;
wait for TIME_DELTA;
slt <= 2;
wait for TIME_DELTA;
slt <= 3;
wait for TIME_DELTA;
slt <= 4;
wait for TIME_DELTA;

END PROCESS;

end ARCHITECTURE Behavioral;

Answer 1

Prompt 35 'restart' and you get a warning that component DUT is not bound. That's legal in VHDL.

Your instantiated component name doesn't match the name of the entity you compiled.

Modelsim has verror that returns an expanded definition of what causes the error:

vsim Message # 3473: The specified component has not been explicitly bound and no default binding has been found for it. This means that your VHDL design does not include a configuration specification or component configuration for the specified component instance in order to indicate the entity/architecture to use for that component. Additionally, no entity of the same name as the component, having ports and generics matching those of the component declaration, was found when searching all visible libraries for a default binding. Simulation can occur, but no VHDL code will be executed for the unbound component instance: it is essentially a null instance.

To cure it you can change name of mux or configure your testbench to use mux for Mwidth_by_by_Ninputs_MUX (DUT). The latter is done with a configuration specification:

signal outp:    std_logic_vector(8 - 1 downto 0);

-- configuration specification added to map mux to Mwidth_by_Ninputs_MUX
    for DUT: Mwidth_by_Ninputs_MUX use entity work.mux;  -- ADDED

begin
--connect DUT
DUT: Mwidth_by_Ninputs_MUX  port map (...

Prompt 36 and you ran the simulation without the DUT. The missing component can't drive your outputs. You non-specifically note the Y output isn't correct (outp is all 'U's, the default initial value). Your waveform format translates those to 'X's.

Fix those and something else will pop up. The default initial value for SLT is INTEGER'LEFT (maximum negative integer value), out of bounds of a in mux.

The declarations for SEL and SLT are at fault and the error is a run time error in mux for the assignment:

y  <= a(sel);

a has a declared range of 0 to 2 ** N -1.

You can constrain the declaration of SEL:

        sel : in integer range 0 to 2 ** n - 1; 

And SLT to match:

signal slt:     integer range 0 to 2 ** 3 - 1;

and now your simulation will complete:

The configuration specification bound mux for DUT (a Mwidth_by_Ninputs_MUX virtual component).

Fixing the range constraints for the SEL and SLT to remain in bounds allows the simulation to run without an a bounds error.