When is proper to use <= or = assigments in Verilog

Question

I have not clear at all this part of Verilog when using <= or when =

I have some always blocks that make some adds, subtracts and multiplies an example is like this:

    module Calcs 
    #
    (
        parameter RC = 24'h0186DA,
                  RV = 24'h018666
    )
    (
        input clk,    // Clock
        //SOME INPUT VALUES FOR VAL1 VAL2 VAL.....

        output reg go  
    );



    reg [63:0] val1; 
    reg [63:0] val2; 

    reg [63:0] val3; 
    reg [63:0] val4; 

    reg [63:0] ValSelected;

    reg [127:0] Mult1; 
    reg [127:0] Mult2; 

    reg [128:0] Subs; 

    reg [128:0] Mult3; 

    reg isNeg;

    reg go1;

    reg [63:0] LastVal1;
    reg [63:0] LastVal2;
    reg [63:0] LastValSelected;

    always @ (posedge clk) begin

         Is_Valid  = (val1 != 0) && (val2 !=0); 


        if (val4 >=  val3) ValSelected = val3; 
        else if (val4 < val3) ValSelected = val4; 

        if (Is_Valid) begin
            Mult1      = val2 * RV;
            Mult2      = val1 * RC;
            Subs       = Mult2 - Mult1;
            isNeg      = Subs < 0;
            if (!isNeg) Mult3 = ValSelected * Subs;
            else Mult3 = 0;
            if (Mult3 > 1) begin
                if (((val1 != LastVal1) || (val2 != LastVal2))  || (ValSelected != LastValSelected)) go1 <= 1'b1;
                else if(((val1 == LastVal1) || (val2 == LastVal2))  || (ValSelected == LastValSelected)) go1 <= 1'b0;           
            end      
        end
    end


    always @ (posedge clk) begin
        if (go1) begin
            LastVal1 = val1;
            LastVal2 = val2;
            LastValSelected = ValSelected;
            go <= 1'b1;
        end
        else go <= 1'b0;
    end
endmodule

There is some strange behavior when I use <= to set the value to go1 this is never executed and if I change this for = this execute always and if the if is fulfilled go1 it never comes back to 0

can someone help me to understand this?

sorry if the code has some issues there is just an example

Many Thanks!

Answer 1

The rule is simply:

If one process writes to a variable synchronized to an event, and another process reads the same variable synchronized to the same event, you must write using an NBA ensuring that the reading process uses the old value of the variable.

If you don't use an NBA writing process, there is a race condition in the reading process in that you don't know if it reads the old or new value.

Note that each always block in your example is both a reading and writing process depending on which variable we are considering synchronized to the posedge clk event. Also consider the processes that write to the module inputs and read the module outputs.

If you have a variable that is local to a process, it is your choice to use either assignment depending on the functionality you desire. But for combinational, blocking assignments are recommended.

Answer 2

Verilog - Blocking Assignment (=) Two Register outputs are assigned the same input, after a shared clk edge.

Verilog – Non-blocking Assignment (<=) Two Register outputs are cascaded, one after the other, after a shared clk edge, I.e. a clock delayed register

As promised, proof that the above is true Ref

Anyone who disagrees must justify.