Verilog: Range must be bounded by constant expression

Question

I have one doubt. The error is: Range must be bounded by constant expression when compiling the below lines:

X=in[i+2 : i] +1'b1;
In[i]=-1;

Please tell how to resolve it.

Answer 1

The width of ranges must be a constant and must be written this way: in[i+:3]

See Accessing rows of an array using variable in Verilog

Answer 2

Remember that Verilog is not a general purpose programming language, it is a hardware description language. Once the hardware is synthesized, or compiled, it generally does not change. So, the code you use to specify the hardware must specify fixed hardware.

Rather than use run-time variables to select the inputs to an adder you must use a multiplexer to select those inputs. The control signals for the multiplexer would be derived from whatever logic you use to choose the value of i in your original code.