VHDL: ADC to USB Buffering using Fifo

Question

I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of making them work together. I do not know the correct approach yet.

I have three vhdl modules adc, ft2232 usb and fifo modules.

1. ADC module is getting samples over spi. Its sample rate is 500KHz.
2. USB module is ft2232h usb implementation where it is achieving around 2 megabytes transfer to pc.
3. Fifo module works as well where i can read and write data on it. I used this code below also tried xilinx's ip core both works. Fifo code

I want to buffer adc samples directly to pc. But what confuses me is that fifo cannot serve to both adc's write and usb's read operations simultaneously. Since they are two seperate processes they might try to use fifo at the same time. Should i define a busy flag to wait during read or write operations.

I appreciate any help.

Answer 1

But what confuses me is that fifo cannot serve to both adc's write and usb's read operations simultaneously.

Sure it can! That's why it has separate write and read ports. They operate completely independently of each other.

Answer 2

Based on our use of Xilinx IP cores I am going to assume you are using a Xilinx FPGA.

Both Xlinx ISE and Vivado have language templates for FIFOs that support reading from one process and writing from another process.

At the hardware level Xilinx FPGAs have 18K/36K bit block RAMs that can be used as FIFOs. The block RAMs have separate read and write ports that can be accessed by different processes (and even different clock domains) at the same time. The Xilinx synthesizers are typically pretty good about inferring the use of block RAMs if you write your FIFO in a way that is similar to the templates in the Synthesis user guides.

In 7-series Xilinx FPGAs you can also use a one LUT-6 primitives to construct small FIFOs up to 64 entries deep. Each LUT-6 can be used as a 64 x 1 bit dual port RAM, so you would used a number of LUT-6 elements equal to the with of your FIFO elements. Again the synthesizer usually infers the LUT-6 based RAM64X1D elements if you code the FIFO according to the Xilinx templates. Similar usage of the LUT-4 elements in older FPGAs should be possible as well.

Most FIFOs have a full/empty flag. You shouldn't need a separate busy flag since concurrent read/write is supported.