I was looking at the TPS63700 DC-DC inverter datasheet and stumbled across the schematic below. It is a more or less usual buck-boost inverter topology schematic, except for the weird R4 and C3 components. I haven't got much experience in SMPS design, however, I've never seen a feedback loop with these components. The datasheet says that
To speed up the control loop, a feed-forward capacitor of 10 pF is recommended in the feedback divider, parallel to R3. To avoid coupling noise into the control loop from the feed-forward capacitor, the feed-forward effect can be bandwidth-limited by adding series resistor R4. A value in the range of 100 kΩ is suitable. The higher the resistance, the lower the noise coupled into the control loop system.
So, my questions:
- What exactly do they mean by "speeding up" the control loop and why or how does it enhance the performance?
- Except for the mentioned induced noise in the feedback circuit, are there any other drawbacks of using this schematic?
- In which SMPS topologies can this feedback quirk be used (especially in high-order ones like SEPIC, Cuk, etc.)?
- Should this feedback quirk be used with other ICs and if not - why?
TPS63700 datasheet link: http://www.ti.com/lit/ds/symlink/tps63700.pdf