How do I find the output impedance of the STM32H743 (and potentially other similar devices)? I've looked through the datasheet (DS12110 Rev 5) and the reference manual (RM0433 Rev 5) however haven't found much information.
I'm mostly interested in the SPI lines, and want to match the track impedance to the output impedance using a series resistor. For now I've put in placeholders of 33R, thinking the PCB trace could be around 50R and the output impedance around 20R.
Output impedance of (typically CMOS) output driver for any MCU can be calculated/estimated from VOH and VOL electrical characteristics from datasheets.
The meaning of this table is that if a 8 mA load is connected to ground and GPIO is driven HIGH, the drop between Vcc and output is 0.4 V. It means that the internal equivalent impedance of GPIO port, per Ohm's Law, 400mV/8mA = 50 Ohms.
Same calculations are valid if the load is connected to Vcc, and the pin is driven to LOW. The table says the residual voltage is no more than 400 mV. Again, it is equivalent to 400/8=50 Ohms or less.
There is one caveat however.
Most MCU have simplified GPIOs, where the impedance depends on load. In this particular case the specifications (same Table 60) says that the voltage drop is 1300 mV if the load takes 20 mA, which makes the output to have roughly 1300/20 = 65 Ohms.
In short, VOH and VOL data at specified load give you an estimation of output impedance of CMOS GPIO driver under 65 Ohms worst case (for STM32H743), and likely close to 40-50 Ohms typical.
If your track's impedance is 70-100 Ohms, you will need to add a 22-33-47 Ohm series resistor at driving side if you want a neat waveform.
It's not common to specify the output impedance of digital logic, because the voltage/current behavior is nonlinear. The best you can do is look for graphs of typical output current vs. output voltage and estimate the slope of the line for your region of interest.
For ST specifically they usually share their IBIS models which are used in simulating high speed lines.
In the datasheet for the STM32H743xI there's a paragraph "Output buffer timing characteristics". They have a table with t[rise] and t[fall] into given capacitive loads at each of the four possible output pin speed settings, where
The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively
From that data you should be able to calculate (estimate) the output impedance.
The output impedance will vary as the output FETs are turned on and then turned off; the operating region is the FET_IN_TRIODE, once the FET is solidly on. In TRIODE, the FET looks like a fairly linear resistor, as long as the voltage excursions are less than 50% of the FET threshold voltage; with Vthreshold of 0.3 volts (an estimate of numerous modern CMOS processes), you can have 0.15 volts reflection and still have a fairly dependable RESISTOR action.
However the output impedance will VARY with temperature, and with VDD, on the PCB. And well or tub or bulk noise will also affect the FET behavior, tho you may not detect this minor delta_Rout.
And as the semiconductor foundary implants atoms to form the Nchannel and Pchannel devices, there will be variations in the conductivity (the output resistance) because thermal annealing will not be precise.
Depending on the exact implanting used, the channel doping may be the DIFFERENCE of two implant cycles, and slight errors of implant-time and spatial fluctuations of implanting because of variations in the plasma-ion-cloud density will be magnified by the differencing.
Summary: you will have to FINETUNE that resistance for every system you ship. IMHO
So ..... keep the edges SLOW; set the slewrate SLOW.
