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I'm working through implementation of the SAP-2 CPU from Digital Computer Electronics, 3rd Edition.

I'm having difficulty understanding how the arithmetic & logical instructions can be implemented in only 4 T-states. Let's take the "ADD B" instruction as an example, which adds the contents of register B to the accumulator (register A).

This CPU design uses 3 T-states to fetch/decode, so the third rising edge latches the instruction into the instruction register from RAM.

That leaves me only one cycle to perform the addition.

Unfortunately, this CPU design also has the ALU hard-connected to the accumulator (A) and a temp register (TMP).

So, I can set up my control word so that on the 4th rising edge it will "enable B" to write to the bus, "load TMP" to receive the value of B, and also set the ALU to addition mode. But, I can't get the sum back out of the ALU and into A during that same rising edge. The data bus is already in use with the B->TMP movement, and the result from the ALU won't be ready yet anyway.

I feel like I'd need a 5th cycle where the control word is set up "enable ALU" & "load A" to store the result back into A, and also set "load flags" to latch the zero and overflow flags.

What am I missing? How does the SAP-2 do all this during just the T4 state?

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  • \$\begingroup\$ Are falling edges also used in the SAP-2? (About which I know nothing at all.) \$\endgroup\$
    – jonk
    Commented Dec 26, 2018 at 22:27
  • \$\begingroup\$ are you sure that there is only one T state after T3 ..... this webpage shows that it may be otherwise .... drghimire.com.np/… \$\endgroup\$
    – jsotola
    Commented Dec 26, 2018 at 22:38
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    \$\begingroup\$ @jsotola Yeah. I looked at the book, Digital Computer Electronics, 3rd edition. It very clearly says that with the SAP-2, the ADD B instruction is 4 T cycles. See Table 11-3. "SAP-2 Instruction Set", the first line of the table. \$\endgroup\$
    – jonk
    Commented Dec 26, 2018 at 22:53
  • \$\begingroup\$ Suppose the ADD is sufficiently decoded on the falling edge of T3 to cause a latch of TEMP from the ALU output latch over the W bus (Or maybe it always does this?) On the rising edge of T4 decoding is complete enough to tristate enable B to the W-bus and set the ALU operation. On the falling edge of T4, latch the ALU output latch with the result (and status.) Just a wild guess. But... \$\endgroup\$
    – jonk
    Commented Dec 26, 2018 at 23:23
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    \$\begingroup\$ @jtdubs It would be nice to see better documentation. That 3rd edition book isn't nearly as good as it could be. \$\endgroup\$
    – jonk
    Commented Dec 27, 2018 at 2:27

1 Answer 1

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Answering my own question here.

The SAP-2 is modeled after the Intel 8080, which also has a 4 cycle ADD instruction.

According to the Intel 8080 System Manual, Table 2-16, during the T4 state of the ADD instruction the accumulator inputs are provided (SSS->TMP, A->ACT) but the result is not written back to the A register.

The write-back to A occurs during the NEXT instruction's T2 state in which Table 2-16 indicates ACT+TMP->A.

This is very likely to be the intended design of the SAP-2 and is simply a detail omitted from the text.

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