Does this circuit adequately represent the thermal considerations for a boost converter?

Question

I'm new to electronics, and I'm trying to use a boost converter to get 5V at 1.2A from a lithium ion battery. I've selected the TPS61232 step up converter for this solution.

The datasheet has a recommended layout:

It's all well and good unless you have a giant inductor (which I have). I tried to capture the concepts of the example layout, but I don't know if I'm missing anything fundamental. Does this look like a rational layout?

I added the vias under the IC which I think are probably dual purpose: heat dissipation and potentially also to wick out some solder so the IC doesn't sit on a solder bubble.

I used a lot of pours which I assumed were to provide additional surface area to dissipate heat.

Finally, I added the vias on the Vout pour, but I'm not sure what those vias are for really.

Additional Details

Here is my current planned BOM:

Inductor Options

Here are some inductors I think I could use and give myself some more space:

• This one seems better in about every way. Lower tolerance, higher DC current, lower DCR, higher SRF (this is good, right?), etc. It's just way more expensive. https://www.mouser.com/ProductDetail/Wurth-Electronics/744316100?qs=sGAEpiMZZMsg%252by3WlYCkUy4%252bqPuxOV5JxsS7NSlX2UA%3d
• My IC has a 2 MHz switching frequency so I feel like I could stand to have a lower SRF. Is that true? Like maybe this one at 50 MHz? https://www.mouser.com/ProductDetail/Bourns/SRP6050CA-1R0M?qs=sGAEpiMZZMsg%252by3WlYCkUwWVs%252bZAfRN3be00zVNyvZQ%3d
• I'm looking to provide 1.2A (my actual output current is quite a bit less really, but I'm looking at 1.2A for the sake of the exercise) at 5V supplying a minimum of 2.8V (from a nearly dead Lithium Ion battery). It looks like my efficiency is going to be somewhere near about 80%. If I call it 70%, then I think it calculates like this . . . my output power is 5V * 1.2A = 6W. With a 70% efficiency I need 8.6W from the supply at 2.8V. So, 8.6W / 2.8V = 3.1A? Well, nevermind . . . after all of that, I don't see any smaller inductors with a lower current rating so it's moot. Still, am I making sense on any of these assumptions?

Implemented changes

Here's what I've done based on (my understanding of) current answers:

• I changed all of the pours (and moved caps) to try to keep pours as straight as possible to avoid bottlenecks.
• I flipped the J2 jumpers around so that the Vout and GND pins will be as close to the output caps as possible. I think that's to reduce the inductance as the current traveled through vias to the other side of the board to get to the ground pin?
• I extended the top side of the board and used .6mm vias with .3mm drill holes to connect Vout to pin 7 so that the ground pour will wrap all the way around the top of the board and provide more direct routes for current to flow to various components.
• I added vias near the ground pin so current to the ground pad can get to the pin more directly (I made this one up myself . . . it might be a bad idea).
• I gave the top ground pour 3mm clearance to increase the surface area slightly.
• I put the ref symbols back because it was dumb to hide them in the first place.

Here's what it looks like at the moment:

Answer 1

Your layout isn't a bad start, but there are some things I would definitely recommend adding before fabricating any boards. Also, your post has nothing that describes your requirements, current load, or environment, so I can only suggest general guidelines that can help. Also, not all of your components have reference designators, so I'll use the datasheet's refs where your are missing.

1) You have solid copper pours for VCC and L1-Pad2, but I don't see the same for ground on Layer 1. I would add solid copper pours between C1 and the thermal pad under the IC, as well as to the caps on the output side. This both allows for more thermal dissipation and lower inductance path for all the switching currents.

EDIT: I see that the ground copper pour is visible in the 3D view - I just don't see if in the 2D view. Based on what I see in the 3D view, I'd recommend widening out the thin neck that goes to C3 on the ground plane a little more space by shifting the output caps (and the VCC plane underneath) south a bit. The VCC plane will still be plenty thick. Same on the other side of the IC - adjust C1 upwards a bit so that the ground plane doesn't have to make a turn, which creates a bottleneck for both current and heat.

2) The vias under the IC should be "Thermal" vias - that, is they are there to carry heat more than to carry current. normally vias are attached to copper pours using a 4-spoke "star" pattern to minimize thermal conductivity, as this makes soldering easier. But for thermal vias, you want a solid connection to the pours (no spokes) to maximize thermal transfer. You'll find a lot with a google search for "thermal via".

Those vias are not there to make sure that the IC doesn't sit on a solder blob. The PCBA manufacturer will create a solder paste stencil that is designed to make sure only the precise amount of solder needed is placed there, no more, no less. Generally, vias which can wick solder away from a pad are a problem, because how much is wicked away is not always predictable. Talk to your manufacturer, they may have a recommendation that you create a "filled" vias - that is, vias that are filled with metal to prevent wicking. They also provide very good thermal contact.

Once you do that, the large ground plane on the bottom of the board will be a good thermal sink.

3) I would shift the L1-Pad2 copper pour to the left a bit to make the "neck" which reaches over to the IC as thick as possible. All of the current through L1 will have to travel through that neck, as it is the only path to the IC. Bottlenecks are unavoidable when routing to IC pins, but make them as short as possible. You can sacrifice a lot of the copper on the VCC pour connecting to L1-Pad2 because most of the current won't flow along the east and northeast edges (because it will from directly from VCC by J1 to L1-Pad2).

4) The vias on the Vout pour are there in case you are connecting to an internal power plane. Many designs will use at least a 4 layer PCB, with the two internal layers being Power and Ground, and the outer two layers are used for trace routing. The area around the power supply will have a lot of surface copper pours, as yours does, but the rest of the board will be full of traces, so the internal layers are used as power planes. In your case, if you are just using a two-layer board to provide 5V on J2, you can just make a direct copper pour connection to J2 with no vias.

5) It looks like you have two, isolated, ground copper pours on the top - one wraps around the bottom of the board and the other is on the top and runs under the IC chip. Although I see that they are connected through vias, I would connect these together directly on the same layer without creating a loop - maybe just shift everything down enough to connect the planes across the top?

6) It would be best if your VOut Caps are referenced to a ground plane connection that is close to the GND pin on your output. Otherwise any current through your caps has to go through the vias to get to your output ground pin. I would shift the entire design south, keep the entire ground planes on the north side, shift your connector north and flip it 180 to make it straddle the same planes as your existing Vout Caps. Not sure if your envelope size constrains you from doing that.

Finally, I'll ask the obvious question: Can you reduce your inductor size? Your inductor should be sized to handle your highest load current plus the ripple current.

Answer 2

To improve your thermal transfer from the IC the other side Gnd plane it is better to use a dozen solder filled micro vias to gain the benefit of 50’C/W rise per sq.in. of 1 oz copper as well as widen the top side channel of Gnd to reduce inductance of about 0.4nH/mm length downward since it operates in MHz region. Saturn PCB design for windows is a must have tool.