Verilog Include Statement Error

Question

I'm trying to teach myself Verilog. I have some previous experience using VHDL. I am using Lattice Diamond as my environment.

I successfully created and simulated a full adder. I now want to use this full adder module to create an 8 bit adder.

The include statement I'm using is

`include "fullAdder.v"

and I get the following error:

2049990 ERROR - EightBitAdder.v(1,10-1,11) (VERI-1055) incorrect use of predefined macro include. Expected "filename"

further down I'm getting errors appearing in the fullAdder source

2049990 ERROR - fullAdder.v(3,1-33,10) (VERI-1206) overwriting previous definition of module fullAdder

I am trying to use the modules as shown below further down in the source file:

    fullAdder adder0(
    .clock      (addClock),
    .a          (a[0]),
    .b          (b[0]),
    .carryIn    (1b'0),
    .sum        (sum0),
    .carryOut   (carry0)
    );

    fullAdder adder1(
    .clock      (addClock),
    .a          (a[1]),
    .b          (b[1]),
    .carryIn    (carry0),
    .sum        (sum1),
    .carryOut   (carry1)
    );
    ...etc

I'm uncertain as to how I should go about fixing this. My searches haven't turned up anything helpful.

Thanks!

Answer 1

You shouldn't need to `include the file at all.

Instead, simply ensure all files are in your project ready to be compiled by your EDA tool. Most (all?) EDA tools will happily compile Verilog without header files.

---

By the looks of it, you have both files being compiled by the EDA tool.

• First it elaborates EightBitAdder.v. You have a `include statement that copies the entire contents of fullAdder.v into it. This means when it compiles the file it now finds a definition of the fullAdder module.
• It then elaborates fullAdder.v, only to find another module called fullAdder. This results in two module definitions with the same name.