Sequence of evaluation in the following non blocking code?

Question

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at cycle 0.

always @ (posedge clk)

A <= 1;
A <= A+1;
B <= A+1;

I understand that the evaluation of RHS is done on the posedge and the assignment happens at the end of the cycle. What value would A have after the assignment? Is it '1' or 'X'?

Also does adding the delay to the statements act as blocking for the following code?

always @ (posedge clk)
begin
#5 A<=1;
#5 A<=A+1;
B <=A+1;
end

Answer 1

I assume there is a begin/end around the three assigment statements. Otherwise the code is legal.

Because you are using non-blocking assignments (NBA) in your first example, A has the old value throughout the current time step. If you have 2 NBA to the same variable in the same timestep, the last one wins. So at the end of the timestep, A has the value A+1. After 5 cycles, it has the value A+5 Since you didn't specify how A gets initialized, that's the best answer you can get. Also realize that your code (enclosed by a single begin/end)is equivalent to

always @ (posedge clk) A <= 1;
always @ (posedge clk) A <= A+1;
always @ (posedge clk) B <= A+1;

In the second example when executing A<=A+1, A already is already updated to its new value, 1, so A would be 2. Note that blocking delays would not be allowed in synthesizable code.