How do you know if impedance is the same for 2 ICs?

Question

in my last question I got some very interesting answers that made rethink a lot about my design as to whether or not I need termination resistors at all. Additionally, the design proposed in this answer as well as the reply in this particular question made me rethink about my approach in general. Now, this is probably going to be a lengthy question, but I hope someone will have the patience to read and clarify things. :)

Background

I am working on a project for sometime now which, among other things, involves the design and implementation of the communication between an FPGA and a USB 3.0 bridge, the MachXO2 and FT601 respectively. It is my first high speed design and I aim to gain experience and insight on the principles of this kind of design.

I have spent last month studying a great amount of literature including resources from here, various other articles from credible sources (like T.I. or questions asked here) as well as Mr. Bogatin's book, "Signal and Power Integrity - Simplified". Due to time contraints, I have not studied in as much depth as I would like, but I think I have got the fundamental ideas. My problem and confusion lies in the application of those.

First Approach

My first approach on the subject was by examining the data I have for both ICs in order to determine whether or not I can get away integrity issued by keeping the traces short enough. FT clocks at 100 MHz but does not provide rise time. On the other side, the MXO2 provides an IBIS file for the design, which reports a rise time of 0.8 ns, which seems rational to use as a rise time for FT too. For 0.8 ns PCB Toolkit reports a max trace length of 1.25 inches. Although I achieved such length, the traces where tightly packed which may introduce significant crosstalk. Additionally, simulation using MXO2 IBIS for my design in Altium revealed significant overshoot and undershoot. Now I understand that this may not be entirely correct since I don't have a proper IBIS for FT, but it got me alarmed anyway.

Terminating R's

In order to be on the safe-side, I decided to use series resistors and terminate the traces with 50Ω. The PCB, of course, is designed in such way that the particular traces have an impedance of 50Ω. I chose that value because FT Configuration Utility lets you config the pin drive strength as 50Ω so we are fine by this driver, and MXO2 drives the lines as 3.3V, 8 mA which roughly translates as 50Ω too by what I have read. Also, the fact that many of the lines are bidirectional perplexes the situation even more. By what I have read, bidir lines must terminate both ways. So, I placed R's in my design both in start and end of the lines, run simulation again and I got some smooth curves. Then I made my previous question.

My Source of Confusion

Now, you may wonder why since both drivers seem to output at 50Ω, did I use the termination scheme. And my answer is because I don't know each receiver's impedance. And this is where the confusion starts for me. Theory and stuff is all good, but I am stuck in the practical application.

According to theory, if Zt, Zr and Z0 are the same (or close) then reflections will not occur. I know Z0 since I designed it, but what about Zt and Zr? And to further complicate things, those lines are bidirectional so they switch functionality.

For the FT, I know it can be 50Ω since you can configure the chip to do so. But although MXO2 at LVCMOS33, 8 mA should have 50Ω too, and IBIS viewer reported that line have actually a lot less like 25-30Ω or so, which complicated matters more for me.

But regardless of the IBIS file (many vendors don't provide one anyway), my confusion sum up to this simple and probably naive questions:

• I have the datasheets of both ICs. Where is it written, implied or can be calculated/extracted the input/output impedance of the pins?

• Is the output impedance the same as input impedance for I/O pins?

• Does the specification of the protocol (in this case LVCMOS33) specifies the I/O impedance?

• How a designer is supposed to know that impedances match between those 2 ICs so a controlled line is all that is required?

Since the design mentioned in my other question does not use R's, then the only reasonable answer I could think of is that probably the whole design is indeed a specific impedance as well as the FPGAs attached to.

All that probably seem quite trivial for an experienced designer, but have really puzzled me for quite some time. If my reputation permitted I would gladly offer a bounty for this question. I did search but I could land to any information.

Answer 1

I didn't read your entire wall of text, but I don't think the answers to your questions depend on much of what you wrote.

I have the datasheets of both ICs. Where is it written, implied or can be calculated/extracted the input/output impedance of the pins?

Different vendors have different conventions for how they report it. One might report an output impedance. One might report an \$|S_{22}|\$ limit. One might report a typical \$S_{22}(f)\$ curve. You'll have to read each individual datasheet and see how they spec their chip.

For some kinds of ICs, input and output impedances aren't specified at all.

Is the output impedance the same as input impedance for I/O pins?

Not necessarily. For a digital buffer, you'd expect input impedance to be very high and output impedance to be very low, for example.

Does the specification of the protocol (in this case LVCMOS33) specifies the I/O impedance?

For CMOS, yes, you can expect a "very low" output impedance, maybe a few ohms. And input impedance will be dominated by capacitance, which will very often be specified.

How a designer is supposed to know that impedances match between those 2 ICs so a controlled line is all that is required?

For CMOS designs, generally you don't match impedances, you just keep the lines short enough that it doesn't matter. A few ohms series resistance on drivers may be used to reduce ringing, but still an actual matched termination is not expected.

One thing I did pick out of your text,

For 0.8 ns PCB Toolkit reports a max trace length of 1.25 inches.

One option is to use a series resistor at the source to increase the rise and fall times. If you increase the edge time to a more reasonable 2 ns (for a 10 ns clock period), you will get a maximum unmatched trace length that's much easier to work with.

Answer 2

This is a point to point link?

Then source termination by the drivers output impedance is probably all you need if you can configure the driver to match the line impedance (which it sounds like you can).

If for example, the driver is 50 ohms and the line impedance is 50 ohms driving a cmos input (so essentially a slightly capacitive open circuit) then you will get almost a 100% reflection at the receiver, which is fine because it will be correctly terminated by the driver output impedance. Note that the double voltage at the receiver compared to the voltage propagating in the line is correct because of the divider formed by the line impedance and the output impedance of the driver, obviously once the reflection arrives at the driver and is terminated the steady state condition applies and line impedance is no longer relevant.

Where this sort of thing goes pearshaped is if you have either a multi drop bus topology or very stiff drivers, either of which will wind up needing some form of termination to get good behaviour, but it does not sound like that is the case here.

Answer 3

There are many ways to interconnect two devices. Depending on timing and speed of connection, you can use a spectrum of connection, starting from single ended unterminated lines, to many sorts of impedance-controlled differential transceivers. I am not sure about Altera, but just get almost any of Xilinx datasheets or I/O design guides, like this one, and you will see whole variety and many available options.