74HC595 Shift Register Latch Pin

Question

I'm picking up a weird bug with my 74HC595 Shift Register's latch pin (Datasheet).

What do I want to do?

I'm essentially trying to visualise the shifting of the bits with the clock constantly running, and varying the serial input. I want to connect a LED to each output pin, and then connect my input clock (555 timer) to the latching pin (RCLK) and serial clock (SRCLK). As far as I understand the output LEDs should then show the state of the shift register, but delayed by one clock cycle, as mentioned in this datasheet:

If both clocks are connected together the input shift register is always one clock cycle ahead of the output register.

What is not working?

Connected the clocks together makes the shifting stop. Nothing shifts through. Not even in the shift registers, as I connected a LED to QH', and it never lights up.

The funny thing is that I could get it to work by unplugging the RCLKpin and letting it float. Then everything works perfectly, and I see my LEDs shifting. This is strange, as a change of state for RCLK is required for latching.

It even works if I place a switch on RCLK. Then I can see the latching only happening at the up and downward edges, as I expect.

But with the RCLKfloating shows the shifting bits perfectly.

My question:

• Am I understanding how the 74HC595 chip works correctly? Is this intended behaviour?
• Does the two input clocks need to be out of phase, as in the timing diagrams?
• Could it just be EMI? It's built on a breadboard, but I put decoupling caps everywhere. Also, the speed I use never more than 2Hz, so I can't imagine that being the problem.

My setup:

My circuit is built on a breadboard, with the following schematic:

Answer 1

Short answer

A wild guess: did you remember to add a 0.1uf capacitor between Vcc and GND, as the 74HC595 datasheet suggests? This makes a huge difference.

Long answer

I just tried something that has a lot in common with what you were doing in your experiment. Here's my configuration

1. I clock my 74HC595 from a 555 timer operating at 1.5 Hz with 50% duty cycle. I.e. nice even square pulses of fairly low frequency.

2. The clock is fed into RCLK and SRCLK shorted together. According to the TI datasheet this a valid mode of operation for 74HC595. It says that in this configuration "the shift register is one clock pulse ahead of the storage register". Fine with me.

3. The SER input is normally pulled down, but can be pulled up by a button. The longer I keep the button depressed, the more 1s is fed into the register as the clock ticks.

4. No input is left floating: everything is either tied to GND or to Vcc.

5. The outputs are connected to 8 LEDs with 470 Ohm resistors in series.

6. The whole assembly is powered by 5V from a regulated PSU.

In this configuration I observed a rather strange behavior.

When I attempted to feed in a single 1 bit (by holding the button down for a fairly short period of time) I got the following sequence of combinations from my diodes, per each clock cycle

*.......
.**.....
...**...
.....**.
.......*

There two strange things here. Firstly, somehow one bit has turned into two bits. (I monitored the clock and the input on an oscilloscope and I knew for sure that I only fed in one bit). Secondly, which is even more strange, each clock cycle the register gets shifted by 2 bits (!) instead on one.

In the next experiment I held the button down for a long time - to fill the entire register with 1s - and then released it. This is what I observed

*.......
***.....   <--- strange
****....
*****...
******..
*******.
********   <--- normal
.*******
..******
...*****
....****
.....***
.......*   <--- strange
........

You can already see the underlying logic behind this behavior: when the number of 1s in the register is low, the register behaves "crazily" and shifts by 2 bits each clock cycle. But once the number of stored 1s gets higher, it suddenly switches to perfectly normal behavior.

I was able to immediately confirm this: if I tried to hold down the button to create a train of 4 sequential 1s, that train shifted through the register in perfectly correct fashion: one bit per clock cycle. No problems whatsoever. Only low-1-bit count patterns made 74HC595 to glitch.

And then I took another look at the datasheet and noticed that I forgot this

The moment I added that capacitor all problems went away.

Answer 2

Although I don't think a can give a full answer to the whole question, just my 2c. I ran into the same issue last weekend, namely sn74hc595n not doing anything if connecting clocks together.

First of all, leaving an input floating is not good. All datasheets say no input must be floating.

As to why your (and mine) 74hc595 did not work with the clocks connected together (even though the datasheet seems to imply it's fine), my current theory is that by connecting the clocks together we're potentially violating the timing requirement regarding SRCLK↑ before RCLK↑: according to the datasheet, it's required that if SRCLK rising edge precedes a RCLK rising edge, SRCLK should not come within 19ns (at 4.5V VCC) of RCLK. By raising both clock signals at the same time, they'll be within 19ns from each other, which breaks the requirement. Granted, if this is true then the datasheet is wrong in implying the clocks can be connected together (or maybe it means something different...). I've found other datasheets (like this toshiba 74hc595) which do not say the clocks can be connected together. So at this point, I'm doubting the accuracy of the TI datasheet. I haven't been able to confirm or rule out this.