Is it possible to make a tri-state bidirectional buffer without any tri-state buffers?

Question

I'm currently making a computer in an application called Smart Logic Simulator. It does not have any tri-state buffers and therefore I cannot make a bus (based off the DM74LS245 chip.) Is there a way to make a tri-state buffer?

EDIT: I don't know much about logic, and it's possible that the thing I want to make isn't a tri-state buffer, but that's what I think it is.

Here are the elements in the app I'm using:

Answer 1

A tristate inverter has truth table:

enable, in, out
0, 0, z
0, 1, z
1, 0, 1
1, 1, 0

You can build such a thing with CMOS transistors. The pull up network has two PMOS in series, and ther pull down network has two NMOS in series. In connects to the lower NMOS and the higher PMOS, and the complement of enable goes to the other two transistors. That looks like this:

^{simulate this circuit – Schematic created using CircuitLab}

You can build other variations on this by introducing inverters in various ways.

Answer 2

I decided to just use Logism. It's much more advanced than what I was using before, and itll make things better such as not having to compensate 2 2-input and gates to make a 4-input and gate. Props to Richard the Spacecat!

Answer 3

Ben Eater's 8-Bit Computer in an online simulator with a TriState Buffer https://electra.academy/simulator/?shared=7736858c77175aa639676e7b4669f0655f0bc727

Simulating this without a special element just by using simple gates is not possible - I think.

Answer 4

In order to implement a high impedance node on a bus, you need a logic-controlled switch that can fully disconnect your peripheral from the network.

Unfortunately, you don't seem to have that here. Every symbol on the page drives the bus either to your high logic voltage level, or to low.

In a real circuit, you can implement this kind of switch with a pair of MOSFETs and another inverter like this example of a tri-state inverting buffer:

^{simulate this circuit – Schematic created using CircuitLab}

The input signal, \$A\$, controls the two outermost MOSFETs. When \$A\$ is high, its connected nMOS conducts; when low, the pMOS conducts. The \$EN\$ signal turns on its connected nMOS when high, and is inverted to turn on its connected pMOS when low. I've drawn the inverter as an inverter here for clarity, but it's really just two more complementary MOSFETs, to make a total of six.

Often, this is simplified as a logic symbol which has a buffer with a third input coming out of the bottom, like so:

Since a symbol like this doesn't appear in your list, you can't really implement tri-state logic.