Verilog code to drive a signal high always

Question

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work.

    reg b;
    always@* 
    begin
       b <= 1'b1; 
    end

b is always 'X' in simulation.

In VHDL, I was able to do similar thing:

signal b: std_logic;
process(all)
begin
b <= '1';
end process;

b is always high in simulation.

I know we can do this using assign statement with wire. But, is it not possible with reg ?

Answer 1

The always block works only if there's something to "trigger" it. In your example, there were no variables on the RHS of any statements, so @* effectively reduces to null.

Of course, initial would have worked just fine ... or always begin (without the @*).

And don't forget that you don't need to use begin/end with always or initial — if you have only a single statement, it's perfectly valid to write

reg b;
initial b <= 1;

or

always @(posedge clock) data_pipe <= data_in;

---

From your comment:

I am just trying to learn the difference between reg and wire types in Verilog. I learnt that 'reg' can be used to design combinational circuits like gates. So I think it does not always mean a register. It can be wires too in hardware.

No, reg does NOT mean "register". It's a very confusing part of Verilog syntax.

Basically, reg variables can be assigned to in process blocks (initial or always statements), while wire variables are assigned to outside such blocks (assign statements, module port connections, etc.)

Answer 2

In Verilog, you can write

reg b = 1;

And then never make another assignment to it. But that's not a good coding strategy. SystemVerilog simplified the rules and does allow a single assign statement to a variable. You should read this article.