I've seen this question: How can I generate a schematic block diagram image file from verilog?, but it talks about verilog, not VHDL. Some answers to that question mention paid tools, and I'm looking exclusively for free, non-commercial tools.
I would like the process to be completely automatic and not manual. I would also like the image to consist purely of logic gates. I've tried researching but I couldn't find anything.
What you're asking for is a two-step process:
HDL (whether that's Verilog or VHDL) to netlist can only be done by a synthesis tool. While there are a few "free" synthesis tools, mostly for specialized applications, most are tied to specific technology vendors.
While converting a schematic to a netlist is fairly straightforward (most any schematic-capture software can produce netlists in a number of formats), converting a netlist into a usable diagram is a hard problem, and I have yet to see a tool, free or otherwise, that does a decent job.
And in the end, such automatically-generated diagrams are rarely useful for any real work anyway.
