Back-to-Back PMOS high power dissipation

Question

I have created a circuit in LTspice to switch between two power sources (10s Li-Ion batteries).

V1 and V3 resemble the power sources which vary from 30-42V. V2 and V3 are output pins of an µC. R3 is a the load.

U1-8 are BBS3002 PMOS with pin1=Drain, pin2=Gate, pin3=Source

It seems to be working, with the exception of a strange high power dissipation in the PMOS (* BBS3002 is the PMOS*) in the following state:

V1=42V, V2=0V, V3=30V, V4=3.3V --> Pd in U1= 8.1 KW

I think it is due to the low voltage drop over U1 and U4, which will open the PMOS in this spice model, altough threshold is at least -1.2V.

Can someone explain to me, what is happening here ?

edit: added PMOS specs (sorry for bad symbol, this is the model from On Semi)

Answer 1

It's still difficult to read the schematic without a real symbol, but I think the problem is you need a negative Vgate-Vsource (i.e. Vgate < Vsource) to turn on a PMOS.

You are either:

1. Discharging the gate-source capacitance through a resistor to turn off

OR

2. Pulling the gate to ground and hoping that the source voltage is positive enough relative to the gate voltage to turn on.

The MOSFET does not care what the gate voltage is (which implicitly means relative to ground). It only cares about the voltage difference between gate and source pins. This is the only voltage it can see anyways.

This can be solved by floating your gate drive so the voltage applied to the gate is relative to the source pin (and not circuit ground). For example, with a separate battery.

Also, when using a MOSFET as a switch you do not care about Vth. That is when it just BARELY starts to turn on. What you care about is the Vgs used to obtain the rated RDson (or look at the Vds-Ids curve and stay in the region where the curve is a straight line).