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I have always used separate always block for infering different flip flops when they dont have much in common.

always_ff@(posedge clk) begin
    if(rst) q1<='0;
    else if(en1) begin
    ......
    end
end

always_ff@(posedge clk) begin
    if(rst) q2<='0;
    else begin
        case(sel)
        ......
        endcase
    end
end

I find it easier to add/modify logic if they are coded in separate always blocks.

I recently read a paper that said :

Each inferred flip-flop should not be independently modeled in its own procedural block/process. As a matter of style, all inferred flip-flops of a given function or even groups of functions should be described using a single procedural block/process. Multiple procedural blocks/processes should be used to model larger partitioned blocks within a given module/architecture. The exception to this guideline is that of follower flip-flops as discussed in section 3.1 where multiple procedural blocks/processes are required to efficiently model the function itself.

Is there a benefit for using single always block or a hazard if we use separate blocks? The only reason I could think of for not using multiple always blocks is(that I have read elsewhere) is it degrades simulator performance.

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    \$\begingroup\$ "not to use separate always blocks for infering flops unless really needed" That is inherently a load of B<censored>T as it would mean that I can not make separate modules but have to write all of the chips 4 million register in one big always block. \$\endgroup\$
    – Oldfart
    Commented Oct 17, 2019 at 7:02
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    \$\begingroup\$ The crux is in the "As a matter of style, ..." which I interpret as: there is no fundamental reason why you should do this. Therefore I don't like statements like that which tell me what my coding style should look like. (p.s. It is better to add the text to your question and remove them from the comments. There is an edit button for that) \$\endgroup\$
    – Oldfart
    Commented Oct 17, 2019 at 8:42
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    \$\begingroup\$ Can you provide a citation for the paper? I disagree with the quoted section, but there may be some context missing. \$\endgroup\$ Commented Oct 17, 2019 at 11:56
  • \$\begingroup\$ @ElliotAlderson ====> This is the link , Page number 6. \$\endgroup\$
    – Pramod
    Commented Oct 18, 2019 at 11:14

2 Answers 2

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Using multiple always blocks will make your code modular, and hence easier to maintain and debug, which is essential when the design gets bigger and complex.

However, it is observed that the increase in number of always blocks slows down the simulation compared to the same logic written in a single always block (See the Source). Otherwise, I dont see any reason why you have to opt out from using multiple always blocks.

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  • \$\begingroup\$ Yes, this is from another paper from same author. That could be the reason why he prefers it to be in a single always block. I just wanted to know if any one style is preferred generally by the community. \$\endgroup\$
    – Pramod
    Commented Oct 18, 2019 at 11:19
  • \$\begingroup\$ But there are limitations like you cannot drive same signal from multiple always block. Once you understand it, you start modularising and maintaining bigger designs with multiple always blocks. \$\endgroup\$
    – Mitu Raj
    Commented Oct 18, 2019 at 11:27
  • \$\begingroup\$ I have read that paper. In fact I like all his papers. You missed to add the context as Elliot pointed out. What he means is if you are modelling two different kind of flip flops, for eg: one with reset and one without reset, you should do it in different always blocks. So that synthesiser will pickout the needed flip-flops from library accordingly. The library contains different types of flip-flops. If you do it in the same always block, synthesiser will not be able to do this as you intended. He's right to the point as I have confirmed it in Vivado thru simple examples. \$\endgroup\$
    – Mitu Raj
    Commented Oct 18, 2019 at 11:37
  • \$\begingroup\$ These situations come for eg. when you have a databus and an associated datavalid signal. You may not want databus to have a reset, but need only data valid to be reset. \$\endgroup\$
    – Mitu Raj
    Commented Oct 18, 2019 at 11:40
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Any decent simulator ought to be able to merge sequential always blocks having common clock and reset inputs, so as to amortize scheduling overhead. At least one EDA vendor does this, and I would not be surprised if they all do.

Write your code for maximum clarity, and let the simulator vendors worry about performance.

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