I need to level shift a 3.3v digital signal to 5.8v at around 1MHz. The circuit below works but the power consumption is very high. Can anyone suggest a modification which will still allow the bandwidth but bring the power consumption down?
Adding resistors to the PFET VCC input and NFET GND output does reduce it but I can't find the right balance between slew rate and consumption.
I've looked at the internals of some off the shelf level shifters but am struggling to understand how they manage it.