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I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "Xmyip_LookupConfig", "Xmyip_CfgInitialize" etc with which I was able to initialize my IP 'myip' and use the function "XAxiDma_SimpleTransfer" to send AXI-stream input data to/from PL/PS.

But if I create any custom-IP (not HLS, but using Create and Package New-IP under tools), in the same name ('myip'), headerfile myip.h (not xmyip.h like in case of HLS) got generated. And also it has the following functions only

#define MYIP2_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))

#define MYIP2_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))

There are no util/wrapper functions ("Xmyip_LookupConfig", "Xmyip_CfgInitialize") like in the case of HLS IP to initialize my IP core. How do I proceed in this case?

Regards

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In that case, you have to write those driver APIs yourself. That's what I have done in the past. Then you have to mention the path of your newly created custom driver files in the driver repositories in SDK and reload and rebuild your BSP.

Note that, it is not mandatory for the drivers to have the same format as Xilinx's AXI IP drivers. In fact, you can live with those two functions that Vivado has given you. Only that's enough actually in most cases to access your IP as it is just a memory mapped peripheral to which you want to either read or write.

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  • \$\begingroup\$ Thanks for the reply. I understand it is just memory mapped, but what about the control signals TVALID, TREADY etc? How am I supposed to do the acknowledgment/handshake part? \$\endgroup\$
    – user3219492
    Commented Nov 20, 2019 at 7:46
  • \$\begingroup\$ All control Registers of your ip are memory mapped which you can access thru AXI. Your IP would have only have AXI signals to talk to processor unless you have modified the top level ports in HDL or have dedicated interrupt pins. \$\endgroup\$
    – Mitu Raj
    Commented Nov 20, 2019 at 8:07
  • \$\begingroup\$ @MituRaj May I ask for sharing the procedure you have used to create the custom driver for custom IP? I have created the .h, .c modules with the driver itself along with the Makefile, .tcl and .mdd files. Unfortunately I was not successful. Thanks. \$\endgroup\$
    – Steve
    Commented May 27, 2020 at 6:45
  • \$\begingroup\$ @Steve I could not find any exact procedure in any vivado guides. What I did was, after generating the IP, I have written my own headers and c files. I looked into the drivers of other Xilinx IPs and wrote my custom driver in similar format. And added this into driver directory of the generated IP. In SDK project you can point to this directory as the driver of your IP. And you can build the project. \$\endgroup\$
    – Mitu Raj
    Commented May 27, 2020 at 7:00
  • \$\begingroup\$ @MituRaj thank you for your reaction. It seems to me that I did the same (although I have been using Vivado and Vitis in versions 2019.2 and my sw is based on FreeRTOS). Despite that I have problems with compilation process. As far as I understand correctly you let the HLS to create default drivers and then you replaced them with your own? Thanks. \$\endgroup\$
    – Steve
    Commented May 27, 2020 at 7:22

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