Transistor sizing in CMOS circuit

Question

Hello, I am currently studying for a digital circuit design course and had a question regarding circuit design here. The sample we were given was unfortunately incomplete and I am not told why this person was wrong here. I know the width sizing (assuming length is constant) of PMOS transistors in CMOS design is ~2.5x the width of NMOS in order to ensure similar current flow and more importantly propagation time, but I am a little confused on how those rules apply to series PMOS/NMOS and parallel PMOS/NMOS.

Am I right to assume that the width of Mpa should be such that the same current flows through that branch as in the parallel branch with Mpc, and thus would need to have double the width of Mpc, 20 microns? And that the width of Mpc is 10 microns because the two 5 micron width PMOS transistors Mpd and Mpe below add up to a 10 micron width transistor in the amount of current that passes through them?

Thank you for any help.

Answer 1

I think the assumption is that all the PFETs are to be adjusted so the overall performance is similar to the NFETs, not just Mpa and Mpc. In parallel, the speed will only be improved, so you have to look at the series combinations. If 2um is the N-type reference and the P equivalent is 5um, we'll assume the Ns are 2um.

Mpc, Mpd and Mpe each have to have half the resistance of the 5um reference since Mpc is in series with either of the others. Therefore they're sized at 10um.

Mpa and Mpb in series combination must match Mpc, so they have half the resistance, or twice the gate width, as Mpc...20um.

As an aside, I'd be asking the prof why I'm using a book that uses units of um instead of nm. Technology marches on.

Answer 2

The width is usually taken as 2.5 times of NMOS for a PMOS transistor in order to compensate the speed of electrons. In this case if the length is also increased on 2.5 times then you are supposed to consider another multiplication factor of 2.5 for the circuit.