The short answer: AFAIK there is no good automatic placement software... yet. Simply because it is enormously complex problem.
The somewhat longer answer: Your expectations are not aligned with the ultimate goal of such software, so even if one such existed you wouldn't be happy with it. The key here is that "All what I want is a working circuit I don't mind the shape ... making routing easier and much faster" only works for prototyping or small hobby projects. Solving complex problem just to accommodate these limited requirements is economically non-feasible. In this old paper found on the web the most interesting part is a huge list of referenced materials, illustrating how many people working on it and for how long.
Finally, the very long answer is that "place the components automatically in the right spot to make routing more efficient" is not the purpose of automatic placement software. At least, not the only one. There are many criteria to be taken into account, for example:
- board size limited by target design (e.g. smart watches);
- board shape and some component locations dictated by form factors (e.g. motherboards);
- interference considerations (e.g. placing decoupling capacitors or separating analog and digital parts)
- thermal distribution considerations;
- high frequency specific requirements (trace matching requires extra space);
- 3-D restrictions between components within the PCB and between PCB and surrounding parts;
- manufacturing considerations (e.g. component "shadowing" during wave soldering);
The above is just a tiny slice of what the software has to know to do its job. The design constraints lists in the existing CAD software already surpassed what average hobbyist is willing to tune-up and yet they do not come even close to what is necessary for fully automatic design.
Now, consider that given small enough grid and sufficient board size the number of component placement permutations even for small projects (like SMPS) quickly grows beyond "brute force" capabilities of modern computers. The same goes for the number of the ways the traces can be routed for each of the placements above. Multiply the two and throw multi-layer options and VIAs into mix and you will get almost infinite choices.
There was a hope that some mathematical method can produce an optimal solution. For example somewhat naive approach of minimizing combined ratsnest distance and number of wire intersections. This quickly turned out to be insufficient. Take a look at the bus routing on any motherboard - if you rip-up those neat parallel traces you would see a crazy mess of air wires, as far as the algorithm is concerned. And yet the "wrong" placement works in the end.
Here is where heuristic methods, like genetic algorithm, come into picture. While not promising optimal placement they can narrow down the choices to something good enough for the final solution. In fact, the chip manufacturers already using these for placement and routing of the integrated circuits. If you think about it, it is not much different from placing and routing of the PCB. Unfortunately, those behemoths poured so much money into development of that software that you are unlikely to see it readily available for the hobbyists any time soon.
