Both approaches are mathematically similar. The below drawing shows how subtracting a voltage ramp from the feedback pin (or adding a negative ramp to the feedback pin) is similar to adding the same ramp to the current-sense information:
In the first case, you reduce the duty ratio by dynamically reducing the setpoint within the switching period. As such, the current sense voltage will meet the toggling point sooner since the setpoint is falling. The comparator trips, imposing a smaller duty ratio than without an external ramp.
In the right-side illustration, the setpoint is fixed but you "accelerate" the ramping voltage by adding another external ramp to it. Similarly as in the above, the resulting waveform will touch the fixed setpoint sooner, effectively reducing the duty ratio.
In both cases, you "fool" the comparator by making it believe there is more voltage developed across the sense resistance \$R_i\$. As you add an artificial ramp \$S_e\$, the modulator gain which is \$G_{PWM}=\frac{1}{(S_e+S_n)T_{sw}}\$ reduces in the current loop path and forces crossover at a lower point where phase margin is improved. As a result, the sub-harmonic poles present in the control-to-output transfer function are damped, reducing the peaking at half the switching frequency.
The \$RCD\$ method you have shown and used in the NCP1200 is a way to produce a quasi-linear ramp from a low-resistance source, the drive output. As such, the ramp can also be of low impedance and the noise immunity of the whole supply improves. This technique - proposed by Ray Ridley in 1990 - was offering a better performance than the solution promoted by Unitrode at that time which consisted of buffering the oscillator ramp and injecting the signal in the CS pin. However, an oscillator deals with low currents and trying to play with this sensitive circuit by adding an emitter follower was often causing problems hence this alternate solution. Modern ICs now either include internal slope compensation or lets you adjust it via a resistance in series with the CS pin (see NCP1250 for instance).
Addendum:
I thought it would be useful to add another sketch with a duty ratio calculation in both cases. In the first one, the ramp subtracts from the setpoint \$V_c\$ imposed by the control loop. In the second case, the ramp is added to the current-sense information and the converter believes there is enough voltage across the sense resistance. Please note that the maximum peak current capability if affected by the amount of injected ramp. It is very likely that the power supply output current capability is reduced once slope compensation is added so something to keep in mind during laboratory experiments:
The below Mathcad sheet shows a quick numerical example for determining how the duty ratio is affected by the injection of an artificial ramp. I took a boost converter in this case. Regardless how you do it - subtract or add - it results with the same duty ratio and peak current. Keep in mind that adding too much ramp to the converter degrades the peak-current-mode operation and turns the control method into a voltage-mode type. Simply put, without ramp, the controller decides to interrupt the switch current based on the inductor current as the ramp is of negligible amplitude but if you add more ramp, then the decision is taken based on the external ramp amplitude (like in voltage mode) more than on the inductor current amplitude as its contribution has become small.
The ramp generated by this circuit with a positive slope is directly injected to the sense current pin of the IC using two resistors to add the inductor current and the ramp signal. 
