Why a CPLD input pin behaves almost like an output pin?

Question

I want my CPLD (a MAX II CPLD, EPM240, see datasheet) to accept an S/PDIF input using an optical receiver with TTL-compatible output.

I tested the receiver alone: when giving proper power and optical connection to an emitter, its output pin shows a nice waveform on the oscilloscope.

But when connecting it to a pin of the CPLD configured as input (pin 44, 3.3-V LVTTL, default) I stop seeing the waveform; instead the signal seems stuck to ~3V. Of course the CPLD receives no data.

Suspecting that the CPLD pin was accidentally configured as an output, I disconnected the receiver and connected the pin to a 10kΩ pull-down resistor. I'd expect almost 3V if it were an output and almost zero if it were an input, instead I measure a voltage of 1.6V which is something in the middle.

So why is the CPLD behaving so weirdly with a digital input, almost behaving like it was configured as output?

Answer 1

Found out that pin 44 was faulty, probably burnt by earlier experiments. Remapping to another pin like pin 52 solved the issue and the signal can now be read.