Deriving the NOT logic gate using PMOS logic

Question

I recently started learning about Field Effect Transistors (FET's) and about the MOS circuit family. From my understanding NMOS is made from a p-type substrate and n-type source/drain, whereas the PMOS is made from a n-type substrate and p-type source/drain. However, I'm not so sure as to how we can derive different logic gates from PMOS and NMOS. Let's say we have the following diagram, where x and y are the inputs and z is the output:

The current in PMOS flows from the Source to the Drain terminal, and that can only happen if the Gate terminal is set to Low. Silly question, but why is that so? Furthermore, how can we use this to get the NOT logic gate (As shown in the second image)?

Answer 1

how can we use this to get the NOT logic gate

Consider this: -

And this (for comparison between using NMOS and PMOS): -

However, most commercial NOT gates use two transistor like this: -

Or this if it helps a little more: -

Answer 2

The current in PMOS flows from the Source to the Drain terminal, and that can only happen if the Gate terminal is set to Low. Silly question, but why is that so?

To answer this question you have to know the working principles of the Mosfet transistor. Generally a PMOS can be turned on if \$ V_{G} \$ < \$ V_{S} \$ and that is because when that kind of voltage is applied to the gate of the PMOS, the electrons present under the oxide layer are pushed downward into the substrate with a repulsive force which leaves us a depletion region populated by donor atoms and just under the oxide we will have a layer of Holes (Which are the charge carriers for PMOS). Then again i strongly suggest that you read these principles yourself.

how can we use this to get the NOT logic gate (As shown in the second image)?

The image that you have provided is a NOT logic gate using NMOS. I'm not sure what you are asking here but if you want to know how it works, it's simple, when the Gate is low, the NMOS is turned OFF, therefore no current flows from Drain to Source so there will be no Voltage across the resistor and output will be equal to VCC(HIGH). If the Gate is high, the NMOS is turned ON and current flows through the NMOS therefore output is connected directly to the ground so the output becomes LOW.

This is the same NOT gate using a PMOS:

^{simulate this circuit – Schematic created using CircuitLab}

Please try and analyze this circuit for yourself.