Circuit Analysis Problem, KCL Nodal Analysis with Supernode

Question

I'm trying to understand how to correctly set the KCL equation for this type of problem that is explained in this ebook at page 19:

I'm following the procedure of the guide, that provides a wrong formula (because it swithces the resistors \$R_1\$ and \$R_2\$ in the formula, this is a minor error that I corrected easily, this is not the problem itself) and not very intuitive; considering a supernode for the voltage source. Since the \$V_{S_1} = 10V\$ we can derive that \$ V_2 = -10 \$. Also for the supernode we can say that \$ V_3 =V1-4 \$. Also the value of resistors are \$R_1 = 4\Omega\$ and \$R_2 = 5\Omega\$.

The KCL formula for the supernode provided by the author is (I'm not considering the resistor switch error): Eq: A.1 $$-I_{S_2}+\frac{V_1}{R_1}+\frac{V_3-V_2}{R_2}-I_{S_1}=0$$ For me from this formula (the results are correct anyway: \$V_1 = -\frac{44}{9}\$) it is not clear how the author is setting the equation:

• The first term \$-I_{S_2} = -(1A)\$ is a current that it is entering the supernode, the author is putting negative sign so is should be a current that is leaving the supernode
• The second term \$\frac{V_1}{R_1}\$ is a current that has a positive sign so it's entering the node, but it is structured as if the current is leaving the node (because the voltage drop is "towards the ground node \$\frac{V_1-0}{R_1}\$" that is different from \$\frac{0-V_1}{R_1}\$).
• The third term has exactly the same structure as the second one, positive sign and the voltage drop "towards" \$V_2\$ so leaving the node.
• The fourth term \$-I_{S_1} = -(-2A)\$ is a negative current that means it is naturally leaving the node, but with a negative sign applied it will have a positive sign that means it is entering.

So the first term is leaving, the second one and the third one are entering with non intuitive voltage drops and the fourth is entering the node

So form this is not clear at all. So I tried to simplify this circuit in the following way: I inverted the \$I_{S_1}\$ current source so that now the negative sign will not confuse anymore and I wanted to set the KCL equation for the supernode assuming all the currents entering the node.

So now the KCL equation for the supernode that I setted is: Eq: M.1 $$I_{S_2}+\frac{0-V_1}{R_1}+\frac{V_2-V_3}{R_2}-I_{S_1}=0$$

In this case we have that:

• The first term \$+I_{S_2}\$ has a positive sign and considering the direction of the current we can say that the current is entering the node.
• The second term \$+\frac{0 - V_1}{R_1}\$ is a current that has a positive sign so it's entering the node, and has a voltage drop "that is towards the supernode" so the current is entering the supernode.
• The third term has the exact same structure as the second with positive sign and the voltage drop "towards or entering the supernode".
• The fourth term \$-I_{S_1}\$ it's normally leaving the node (considering the direction of the current) so now applying a negative sign the current is entering the supernode. Substituting the numbers I got the correct result in Eq: M.1: $$+1+\frac{0-V_1}{4}+\frac{V_2-V_3}{5}-2=0$$ $$+20-5V_1+4(-10)-4(V_1-4)+20(-2) = 0$$ $$V_1 = -\frac{44}{9}$$

My doubts come now: since with KCL and nodal analysis I can make the wrong assumptions about the direction of the currents and still getting the correct results, this not seems the case infact:

• Considering all currents leaving the supernode, the equation Eq: M.2 should be the following $$-1 -\frac{V_1-0}{4} - \frac{V_3-V_2}{5} + 2 = 0$$ the result it will give \$V_1=-\frac{4}{9}V\$. The same will happen if I consider any other approaches that are different from considering all the currents entering the node. We can see that we have a different solution also from a calculator

My question is: why is this happening (I can normally set KCL equation as I like and always get the correct result)? Is there something that I should consider when dealing with supernodes)? Why the ONLY correct result is when I set all the currents ENTERING the supernode?

Any suggestion are welcomed. Thank You

Answer 1

Approach

Always get into the practice of re-drawing the schematic (see Appendix below):

^{simulate this circuit – Schematic created using CircuitLab}

There's no need to show current source/sink terminals that are tied to a known voltage source (since they cannot affect its voltage.) So I just don't show that, as it's not necessary.

You already know that \$V_3=V_1-4\:\text{V}\$. So you only need to solve for \$V_1\$ (or \$V_3\$, but not both) and also the current through \$V_{s_2}\$, namely \$I_{V_{s_2}}\$. So you only have two equations to develop:

$$\begin{align*} \begin{array}{c} {\text{Node } V_1:}\vphantom{\frac{V_1}{R_1}}\\\\ {\text{Node } V_3:}\vphantom{\frac{V_1}{R_1}} \end{array} && \overbrace{ \begin{array}{r} \frac{V_1}{R_1} + I_{V_{s_2}}\\\\ \left[\frac{V_3}{R_2} + I_{s_1}=\frac{V_1-4\:\text{V}}{R_2} + I_{s_1}\right] \end{array} }^{\text{outflowing currents}} & \begin{array}{c} &\quad{=}\vphantom{\frac{V_1}{R_1}}\\\\ &\quad{=}\vphantom{\frac{V_1}{R_1}} \end{array} & \overbrace{ \begin{array}{l} I_{s_2}\\\\ \frac{V_2}{R_2}+I_{V_{s_2}} \end{array} }^{\text{inflowing currents}} \end{align*}$$

(See KCL Addendum below if the above isn't instantly obvious.)

That's all there is to it. Nothing terribly confusing.

Appendix

One of the better ways to try and understand a circuit that at first appears to be confusing is to redraw it. There are some rules you can follow that will help get a leg-up on learning that process. But there are also some added personal skills that gradually develop over time, too.

I first learned these rules in 1980, taking a Tektronix class that was offered only to its employees. This class was meant to teach electronics drafting to people who were not electronics engineers, but instead would be trained sufficiently to help draft schematics for their manuals.

The nice thing about the rules is that you don't have to be an expert to follow them. And that if you follow them, even blindly almost, that the resulting schematics really are easier to figure out.

The rules are:

• Arrange the schematic so that conventional current appears to flow from the top towards the bottom of the schematic sheet. I like to imagine this as a kind of curtain (if you prefer a more static concept) or waterfall (if you prefer a more dynamic concept) of charges moving from the top edge down to the bottom edge. This is a kind of flow of energy that doesn't do any useful work by itself, but provides the environment for useful work to get done.
• Arrange the schematic so that signals of interest flow from the left side of the schematic to the right side. Inputs will then generally be on the left, outputs generally will be on the right.
• Do not "bus" power around. In short, if a lead of a component goes to ground or some other voltage rail, do not use a wire to connect it to other component leads that also go to the same rail/ground. Instead, simply show a node name like "Vcc" and stop. Busing power around on a schematic is almost guaranteed to make the schematic less understandable, not more. (There are times when professionals need to communicate something unique about a voltage rail bus to other professionals. So there are exceptions at times to this rule. But when trying to understand a confusing schematic, the situation isn't that one and such an argument "by professionals, to professionals" still fails here. So just don't do it.) This one takes a moment to grasp fully. There is a strong tendency to want to show all of the wires that are involved in soldering up a circuit. Resist that tendency. The idea here is that wires needed to make a circuit can be distracting. And while they may be needed to make the circuit work, they do NOT help you understand the circuit. In fact, they do the exact opposite. So remove such wires and just show connections to the rails and stop.
• Try to organize the schematic around cohesion. It is almost always possible to "tease apart" a schematic so that there are knots of components that are tightly connected, each to another, separated then by only a few wires going to other knots. If you can find these, emphasize them by isolating the knots and focusing on drawing each one in some meaningful way, first. Don't even think about the whole schematic. Just focus on getting each cohesive section "looking right" by itself. Then add in the spare wiring or few components separating these "natural divisions" in the schematic. This will often tend to almost magically find distinct functions that are easier to understand, which then "communicate" with each other via relatively easier to understand connections between them.

The above rules aren't hard and fast. But if you struggle to follow them, you'll find that it does help a lot.

KCL Addendum

The KCL equations may appear to treat node voltages as if they don't have to be differences, but can be absolute values. However, that's not really the case here. In fact, I'm just using superposition (which is easily seen once you've really had the concepts deepened into you.) This is, in fact, the same technique used within Spice programs (those where I've directly looked over the code used to generate these.)

Perhaps the easiest way to imagine is that absolute voltage at a node spills away from that node through the available paths. But also that absolute voltages spill into that node from surrounding nodes through those same paths. So long as you treat them all as absolute values, the result is the application of a simple superposition concept that results in, effectively, the potential differences controlling the result.

You can test this, easily, by rearranging the resulting equation(s), moving the right side over to the left side and then combining terms. You'll then see the usual potential differences that you expect. So it really is the same result.

The reason I very much prefer this method is that it is simple to visualize and very difficult to make mistakes. You can easily orient yourself to a node and then work out the terms for out-flowing currents for the left side of the equation. Then all you have to do is position yourself at each surrounding node and work out the terms for in-flowing currents for the right side. It's almost impossible to screw that up.

Conversely, when you are instead struggling to work out the potential differences in your mind (using the more traditionally taught method) and just write those terms, you often find yourself not entirely sure if you have the sign right as you try and add them up, correctly. I find, time and time again that not only others wind up messing up somewhere and making an uncaught mistake.. but that I also make those mistakes, as well. Even with lots of experience, you just aren't 100% sure and you often find yourself double and triple checking your work, just in case.

That doesn't ever happen, once you start using the superposition method. It just works. It just works right. It just works right each and every time. I've never, not once, screwed up. (I make typos. But not sign errors.) It's too easy to use.

So voltage spills away from a node via available paths and voltage spills into a node from nearby nodes via the same available paths. The only caveat is that a current source or sink can only flow in, or flow out, but not both directions. It's one way. So it will either appear on the out-flowing side or on the in-flowing side -- but not both sides.

This also works perfectly well with capacitors and inductors. It does turn the equation into a differential/integral equation. But that's just a technicality. It's still correct.