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I'm programming a blackboard using Verilog. The hardware information is provided in the link above.

My goal is to light up the seven-segment display such that I can see characters on the segment display after programming. I would like to add the option of turning the display off at the push of a button, but I need to overcome the issue of lighting up the display with different characters first.

I'm a student learning to program and I thought of achieving my goal by studying the schematic. I found that if I could manage to do the following:

  • b0001000 (turn "off" D, should display A)

  • b0100100 (turn "off" B and E, should display S)

  • b0110000 (turn "off" all except B and C, should display I)

The problem I saw was that all four segments displayed the same items.

I found this forum to be very helpful as far as providing information but I have trouble understanding because I'm still learning all the terms. One of the post mentioned multiplexing and charlieplexing, and I understand the concept just not how to implement said idea into the device. I feel like the answer is staring me in the face, but IDK.

Additionally, in the 3rd link from the top it seems that I may be able to control the displays using the following: SVN_SEG_DATA (0x43C10004 - 0x43C10010) but that's as far as my brain got.

Any help would be greatly appreciated, thank you!

https://www.realdigital.org/hardware/blackboard

https://www.realdigital.org/doc/586fb4c3326dcd493a5774b2a6050f41

https://www.realdigital.org/doc/ad0c5fbdaddde0e930abbd9eda84f88b

How to display character on multiplexed seven segment?

`timescale 1ns / 1ps


module Seven_segment_LED_Display_Controller(

output [3:0]seg_an,
output [7:0] seg_cat
//input  btn
);


//assign seg_an = btn;
//assign seg_an[1] = seg_an[0];
//assign seg_an[2] = seg_an[0];
//assign seg_an[3] = seg_an[0];

assign seg_an[0] = ~seg_cat[0] & ~seg_cat[1] & ~seg_cat[2] & seg_cat[3] & ~seg_cat[4] & ~seg_cat[5] & ~seg_cat[6] & seg_cat[7];
assign seg_an[1] = ~seg_cat[0] & seg_cat[1] & ~seg_cat[2] & ~seg_cat[3] & seg_cat[4] & ~seg_cat[5] & ~seg_cat[6] & seg_cat[7];
assign seg_an[2] = ~seg_cat[0] & seg_cat[1] & seg_cat[2] & ~seg_cat[3] & ~seg_cat[4] & ~seg_cat[5] & ~seg_cat[6] & seg_cat[7];
assign seg_an[3] = seg_an[0];

endmodule
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  • \$\begingroup\$ I would think you'd be getting a compiler error here. Your seg_cat is an output yet you're reading it during your assign statement. That shouldn't be legal. And if it is an output you're never assigning anything to it. \$\endgroup\$
    – td127
    Commented Sep 27, 2020 at 21:57

1 Answer 1

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What you want to do:

  • Put a pattern onto your seg_cat pins
  • Pull just one of your seg_an pins low
  • Wait a while -- this needs to be slow enough so that the electronics have time to react, and fast enough so that you don't see flicker. Figure that if you refresh the display at 50Hz or faster, you're fine -- that means about 5ms per digit. This is slow for an FPGA.
  • Pick a different pattern & seg_an pin, and repeat

What you are doing:

  • Pick some random pattern of seg_cat pins
  • Pull all of the seg_an pins low (probably -- because you're anding individual seg_cat pins).

It gets really open-ended from here, but you need to have a delay module that outputs a trigger pulse once every 5ms. You need to have a sequencing module that takes that trigger pulse as an input and advances the state of the seg_an pins (or that counts out a state from 0 to 3 and repeat), you need a module to drive the appropriate seg_an pin low, and you need a module to put the correct pattern out on the seg_cat pins.

You can do this all in one module if you don't mind being messy -- but I can tell you now that you should have an "always @posedge clock" in there, and a counter, and something that keeps track of which digit should be lit up at any given moment.

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  • \$\begingroup\$ Thank you very much Tim! So I think this is how I should go about it. ``` //after module declaration. always @ (btn) begin always @ posedge (clock) begin while (btn == true) case (0) seg_an[0] = 7b0001000; case (1) seg_an[1] = 7b0100100; case (2) seg_an[2] = 7b0110000; case (3) seg_an[3] = 7b0001000; default = 7`b1111111; end wait using the command #value I think. end endmodule ``` This is the rough concept and I will be refining it as I go. Like I said the implement part will be a learning experience. I am grateful for your help by the way. \$\endgroup\$
    – Jack Vidal
    Commented Sep 28, 2020 at 17:12
  • \$\begingroup\$ My comment is a mess. Once I have it taken care of I will post an answer to my question or edit my question once I arrive to the result I'm seeking. Thanks again Tim! I have my road set out for me. \$\endgroup\$
    – Jack Vidal
    Commented Sep 28, 2020 at 17:30
  • \$\begingroup\$ I think you're on the right track. \$\endgroup\$
    – TimWescott
    Commented Sep 28, 2020 at 17:38

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