I want to design a SDI-12 interface and I am using this schematic as a starting point. In receive mode, the 5V SDI-12 data signal will reach UART RX via the transistor Q1, but will also reach the output of the buffer U1 (I my case, it is a 74LV1T126GVH).
So, is there a risk of damaging the buffer when applying the RX voltage on its output? If so, what solution is there to this problem?
The buffer will not work. And the schematic violates some of SDI-12 tranceiver requirements, such as DC impedance to GND.
The buffer will also not tolerate 5V on output if it is unpowered (VCC=0), so it will load down the bus outside the allowed limits of SDI-12 specs.
It needs an inverting buffer like in the example schematics, unless the UART_TX polarity can be set in the MCU. Sometimes UART polarity can be set, but is it separate for TX and RX is another question. As it is now, UART_TX and UART_RX will have opposite polarity, as the FET inverts the data.
Otherwise the schematic is almost a copy of reference design from SDI-12 standard.
What you need is Tri-state buffers.
When one output or one input is not in use, it can be set as high impedance with the EN or -OE pins. And so the input or output is protected up to Vcc or even sometimes above that.
